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參數(shù)資料
| 型號(hào)： | IDT7M1002S45GB |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 16K X 32 MULTI-PORT DEVICE SRAM MODULE, 45 ns, CPGA121 |
| 封裝： | CERAMIC, PGA-121 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | IDT7M1002S45GB |
7.02
10
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH
BUSY
INPUT (M/
S
≤
VIL)
2795 drw 13
t
WP
t
WH
t
WB
BUSY
DATA
INR
R/
W
TIMING WAVEFORM OF BUSY ARBITRATION (
CS
CONTROLLED TIMING)
(1)
2795 drw 14
t
BDC
ADDR "A"
AND "B"
t
APS(2)
t
BAC
ADDRESS MATCH
CS
"B"
CS
"A"
BUSY
"B"
ADDR"B"
2795 drw 15
t
BDA
ADDR "A"
t
BAA
ADDRESS "N"
t
APS(2)
MATCHING ADDRESS "N"
BUSY
"B"
NOTES:
1. All timing is the same for the left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t
APS
is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
TIMING WAVEFORM OF BUSY ARBITRATION (CONTROLLED BY ADDRESS MATCH TIMING
(1)
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