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參數(shù)資料
| 型號： | IDT7M1014S25GB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 4K x 36 BiCMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 4K X 36 MULTI-PORT DEVICE SRAM MODULE, 25 ns, CPGA142 |
| 封裝： | CERAMIC, PGA-142 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 85K |
| 代理商： | IDT7M1014S25GB |
7.03
7
IDT7M1014 4K x 36 BiCMOS
DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE (EITHER SIDE)
(1,2)
NOTES:
1. R/
W
is HIGH during all address transitions.
2. If
OE
is LOW during the write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn
off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH, this requirement does not apply, and the write pulse
can be as short as the specified t
WP
.
3. This parameter is guaranteed by design but not tested.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
2819 drw 08
DATA
OUT
t
AW
t
DW
DATA
IN
R/
W
OE
ADDRESS
t
WC
t
DH
t
OHZ
t
AS
t
WP
t
WR
t
WHZ
t
OW
(4)
(4)
DATA VALID
(3)
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