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參數(shù)資料
| 型號(hào)： | IDT821054PQFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 1/45頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCM CODEC QUAD MPI 64-PQFP |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | PCM 音頻接口 |
| ADC / DAC 數(shù)量： | 4 / 4 |
| 三角積分調(diào)變： | 無(wú) |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-QFP |
| 供應(yīng)商設(shè)備封裝： | 64-PQFP（14x14） |
| 包裝： | 管件 |
| 其它名稱： | 800-2516-5 821054PQFG IDT821054PQFG-ND |
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1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
FEBRUARY 26, 2003
DSC-6035/5
FEATURES
4-channel CODEC with on-chip digital filters
Software selectable A/-law, linear code conversion
Meets ITU-T G.711 - G.714 requirements
Programmabledigitalfiltersadaptingtosystemdemands:
- AC impedance matching
- Transhybrid balance
- Frequency response correction
- Gain setting
Supports two programmable PCM buses
Flexible PCM interface with up to 128 programmable time slots,
data rate from 512 kbits/s to 8.192 Mbits/s
MPI control interface
Broadcast mode for coefficient setting
7 SLIC signaling pins (including 2 debounced pins) per channel
Fast hardware ring trip mechanism
2 programmable tone generators per channel for testing,
ringing and DTMF generation
1 programmable FSK generator for sending Caller-ID messages
Two programmable chopper clocks
Master clock frequency selectable: 1.536 MHz, 1.544 MHz, 2.048
MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or
8.192 MHz
Advanced test capabilities:
- 3 analog loopback tests
- 5 digital loopback tests
- Level metering function
High analog driving capability (300
AC)
TTL/CMOS compatible digital I/O
CODEC identification
+5 V single power supply
Low power consumption
Operating temperature range: -40
°C to +85°C
Package available: 64 Pin PQFP
FUNCTIONAL BLOCK DIAGRAM
Filter and A/D
D/A and Filter
SLIC Signaling
CH1
VIN1
VOUT1
2 Inputs
3 I/Os
2 Outputs
CH2
DSP
Core
CH4
General Control
Logic
PLL and Clock
Generation
PCM Interface
RESET INT12
DR2
DX1
MCLK
CHCLK1
CHCLK2
FS BCLK
Filter and A/D
D/A and Filter
SLIC Signaling
CH3
2 Inputs
3 I/Os
2 Outputs
VIN3
VOUT3
MPI Interface
CCLK
CI CO
CS
INT34
TSX2
TSX1
DR1
DX2
QUAD PROGRAMMABLE PCM
CODEC WITH MPI INTERFACE
IDT821054
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