參數(shù)資料
型號(hào)： IDT82P20516DBFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 55/115頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝： 84
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 16
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.89W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-LFBGA
供應(yīng)商設(shè)備封裝： 484-CABGA（19x19）
包裝： 托盤
包括： AIS 警報(bào)檢測(cè)器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測(cè)器，遠(yuǎn)程檢測(cè)器和發(fā)生器
IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Functional Description
44
December 17, 2009
3.5.8.2 Jitter Measurement (JM)
The RJA of channel 0 consists of a Jitter Measurement (JM) module.
When the RJA is enabled in channel 0, the JM is used to measure the
positive and negative peak value of the demodulated jitter signal of the
received data stream. The bandwidth of the measured jitter is selected
by the JM_BW bit (b0, JM).
The greatest positive peak value monitored in a certain period is indi-
cated by the JIT_PH and JIT_PL registers, while the greatest negative
peak value monitored in the same period is indicated by the JIT_NH and
JIT_NL registers. The relationship between the greatest positive /nega-
tive peak value and the indication in the corresponding registers is:
Positive Peak = [JIT_PH, JIT_PL] / 16 (UIpp);
Negative Peak = [JIT_NH, JIT_NL] / 16 (UIpp).
The period is determined by the JM_MD bit (b1, JM).
When the JM_MD bit (b1, JM) is ‘1’, the period is one second auto-
matically. The one-second timer uses MCLK as clock reference. The
expiration of each one second will set the TMOV_IS bit (b0, INTTM) and
induce an interrupt reported by INT if not masked by the TMOV_IM bit
(b0, GCF). The TMOV_IS bit (b0, INTTM) is cleared after a ‘1’ is written
to this bit. When each one second expires, internal buffers transfer the
greatest positive/negative peak value accumulated in this one second to
the JIT_PH and JIT_PL / JIT_NH and JIT_NL registers respectively and
the internal buffers will be cleared to start a new round measurement.
The registers should be read in the next second, otherwise they will be
overwritten. Refer to Figure-27 for the process.
When the JM_MD bit (b1, JM) is ‘0’, the period is controlled by the
JM_STOP bit (b2, JM) manually. When there is a transition from ‘0’ to ‘1’
on the JM_STOP bit (b2, JM), the internal buffers transfer the greatest
positive/negative peak value accumulated in this period to the JIT_PH
and JIT_PL / JIT_NH and JIT_NL registers respectively and the internal
buffers will be cleared to start a new round measurement. The registers
should be read in the next round of jitter measurement, otherwise they
will be overwritten. Refer to Figure-28 for the process.
Figure-27 Automatic JM Updating
Figure-28 Manual JM Updating
Read the JIT_PH, JIT_PL & JIT_NH,
JIT_NL registers in the next second
TMOV_IS is cleared after a '1' is written to it
The greatest peak value in the internal
buffers transfers to the JIT_PH & JIT_PL /
JIT_NH & JIT_NL registers respectively
The internal buffers are cleared
One second expired?
(TMOV_IS = 1 ?)
Peak jitter measurement
Automatic JM Updating
(JM_MD = 1)
No
Yes
repeat the
same
process in
the next
second
Read the JIT_PH, JIT_PL & JIT_NH,
JIT_NL registers in the next round
The greatest peak value in the internal
buffers transfers to the JIT_PH & JIT_PL
/ JIT_NH & JIT_NL registers respectively
The internal buffers are cleared
A transition from '0' to
'1' on JM_STOP ?
Peak jitter measurement
Manual JM Updating
(JM_MD = 0)
No
Yes
repeat the
same
process in
the next
round
(JM_STOP
must be
cleared
before the
next round)
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