參數(shù)資料
型號(hào)： IDT82P2282PK
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 數(shù)字傳輸電路
英文描述： Dual T1/E1/J1 Long Haul / Short Haul Transceiver
中文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 71/375頁(yè)
文件大?。?/td> 2430K
代理商： IDT82P2282PK
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)當(dāng)前第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)第320頁(yè)第321頁(yè)第322頁(yè)第323頁(yè)第324頁(yè)第325頁(yè)第326頁(yè)第327頁(yè)第328頁(yè)第329頁(yè)第330頁(yè)第331頁(yè)第332頁(yè)第333頁(yè)第334頁(yè)第335頁(yè)第336頁(yè)第337頁(yè)第338頁(yè)第339頁(yè)第340頁(yè)第341頁(yè)第342頁(yè)第343頁(yè)第344頁(yè)第345頁(yè)第346頁(yè)第347頁(yè)第348頁(yè)第349頁(yè)第350頁(yè)第351頁(yè)第352頁(yè)第353頁(yè)第354頁(yè)第355頁(yè)第356頁(yè)第357頁(yè)第358頁(yè)第359頁(yè)第360頁(yè)第361頁(yè)第362頁(yè)第363頁(yè)第364頁(yè)第365頁(yè)第366頁(yè)第367頁(yè)第368頁(yè)第369頁(yè)第370頁(yè)第371頁(yè)第372頁(yè)第373頁(yè)第374頁(yè)第375頁(yè)
IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
60
October 7, 2003
3.18
TRANSMIT SYSTEM INTERFACE
The Transmit System Interface determines how to input the data to
the device. The timing clocks and framing pulses can be provided by the
system backplane or obtained from the processed data. The Transmit
System Interface supports various configurations to meet various
requirements in different applications.
3.18.1
T1/J1 MODE
In T1/J1 mode, the Transmit System Interface can be set in Non-
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSD pin is used to input the data at the bit rate of 1.544 Mb/s or
2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed Mode, the
data is byte-interleaved from one high speed data stream and inputs on
the MTSD pin at the bit rate of 8.192 Mb/s. The demultiplexed data input
to the link is 2.048 Mb/s on the system side and converted into 1.544
Mb/s format to the device.
In the Non-multiplexed mode, if the transmit system interface and
the transmit line side are timed to a same clock source, the Transmit
System Interface is in Transmit Clock Master mode. If the transmit sys-
tem interface and the transmit line side are timed to different clock
sources, the Transmit System Interface is in Transmit Clock Slave
mode.
In the Transmit Clock Master mode, if TSCK outputs pulses during
the entire T1/J1 frame, the Transmit System Interface is in Transmit
Clock Master Full T1/J1 mode. If only the clocks aligned to the selected
channels are output on TSCK, the Transmit System Interface is in
Transmit Clock Master Fractional T1/J1 mode.
In the Transmit Clock Slave mode, the backplane data rate may be
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s. If the back-
plane data rate is 2.048 Mb/s, the Transmit System Interface is in T1/J1
mode E1 rate and the data to be transmitted should be mapped to 1.544
Mb/s per 3 kinds of schemes.
In the Transmit Multiplexed mode, since the demultiplexed data
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), there are still 3 kinds of schemes to be
selected.
Table 42 summarizes how to set the transmit system interface into
various operating modes and the pins’ direction of the transmit system
interface in different operating modes.
3.18.1.1
Transmit Clock Master Mode
In the Transmit Clock Master mode, the timing signal on the TSCK
pin and framing pulse on the TSFS pin are used to input the data on the
TSD pin. The signaling bits on the TSIG pin are per-channel aligned with
the data on the TSD pin.
In the Transmit Clock Master mode, the data on the system inter-
face is clocked by the TSCK. The active edge of the TSCK used to
update the pulse on the TSFS is determined by the FE bit. The active
edge of the TSCK used to sample the data on the TSD and TSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFS is ahead.
In the Transmit Clock Master mode, the TSFS can indicate each F-
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFS is selected by the FSINV bit.
The Transmit Clock Master mode includes two sub-modes: Trans-
mit Clock Master Full T1/J1 mode and Transmit Clock Master Fractional
T1/J1 mode.
3.18.1.1.1
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCK is a stan-
dard 1.544 MHz clock, and the data in the F-bit and all 24 channels in a
standard T1/J1 frame are clocked in by the TSCK.
Transmit Clock Master Full T1/J1 Mode
Table 42: Operating Modes Selection In T1/J1 Transmit Path
TMUX TMODEGFBITGAP
MAP[1:0]
2
Operating Mode
Transmit System Interface Pin
Input
Output
0
0
00 / 0
not all 0s
1
X
Transmit Clock Master Full T1/J1
Transmit Clock Master Fractional T1/J1
TSD, TSIG
TSCK, TSFS
1
X
00
01
Transmit Clock Slave - T1/J1 Rate
Transmit Clock Slave - T1/J1 Mode E1 Rate per G.802
Transmit Clock Slave - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per G.802
Transmit Multiplexed - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
TSD, TSIG, TSCK, TSFS
X
10
11
01
1
X
X
MTSCK, MTSFS, MTSD,
MTSIG
X
10
11
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Transmit Multiplexed mode.
相關(guān)PDF資料
PDF描述
IDT82P2288BB Octal T1/E1/J1 Long Haul Short Haul Transceiver
IDT82V2088BB OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT
IDT82V2058DA OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
IDT82V2608BB INVERSE MULTIPLEXING FOR ATM
IDT82V2608 INVERSE MULTIPLEXING FOR ATM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82P2284 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Quad T1/E1/J1 Long Haul / Short Haul Transceiver
IDT82P2284BB 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82P2284BB8 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82P2284BBG 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:驅(qū)動(dòng)器 驅(qū)動(dòng)器/接收器數(shù):4/0 規(guī)程:RS422 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC N 包裝:帶卷 (TR)
IDT82P2284BBG8 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*