參數(shù)資料
型號(hào)： IDT82P2284BB8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 296/363頁(yè)
文件大小： 0K
描述： TXRX T1/J1/E1 4CHAN 208-PBGA
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
規(guī)程： T1，E1，J1
電源電壓： 1.8V, 3.3V
安裝類型： 表面貼裝
封裝/外殼： 208-BGA
供應(yīng)商設(shè)備封裝： 208-PBGA（17x17）
包裝： 帶卷 (TR)
其它名稱： 82P2284BB8
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IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
38
February 25, 2008
3.8.1.2 Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor continues
to monitor the received data stream to detect errors and judge if it is out
of synchronization.
Super Frame (SF) Format
In SF format, two kinds of errors are detected:
Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 12). Each unmatched Ft bit leads to
an Ft bit error event. When 2 or more Ft bit errors are detected in a
6-basic-frame fixed window, the severely Ft bit error occurs. This
error event is captured by the SFEI bit.
F Bit Error: Each received F bit is compared with the expected one
(refer to Table 12). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is for-
warded to the Performance Monitor.
When the F Bit Error number exceeds the ratio set in the M2O[1:0]
bits, it is out of synchronization. Then if the REFEN bit is ‘1’, the Frame
Processor will start to search for synchronization again. If the REFEN bit
is ‘0’, no error can lead to reframe except for manually setting. The
manual reframe is executed by a transition from ‘0’ to ‘1’ on the REFR
bit. During out of synchronization state, the error event detection is
suspended.
Once resynchronized, if the new-found F bit position differs from the
previous one, the change of frame alignment event is generated. This
event is captured by the COFAI bit and is forwarded to the Performance
Monitor.
Extended Super Frame (ESF) Format
In ESF format, four kinds of errors are detected:
Frame Alignment Bit Error: Each received Frame Alignment bit is
compared with the expected one (refer to Table 13). Each
unmatched bit leads to a frame alignment bit error event. This error
event is captured by the FERI bit and is forwarded to the Perfor-
mance Monitor.
CRC-6 Error: When the local calculated CRC-6 of the current
received ESF frame does not match the received CRC-6 of the
next received ESF frame, a single CRC-6 error event is generated.
This error event is captured by the BEEI bit and is forwarded to the
Performance Monitor.
Excessive CRC-6 Error: Once the accumulated CRC-6 errors
exceed 319 occasions (> 319) in a 1 second fixed window, an
excessive CRC-6 error event is generated. This error event is cap-
tured by the EXCRCERI bit and is forwarded to the Performance
Monitor.
Severely Frame Alignment Bit Error: When 2 or more frame align-
ment bit errors are detected in a 1-ESF-frame fixed window, the
severely frame alignment bit error occurs. This error event is cap-
tured by the SFEI bit.
When the Frame Alignment Bit Error number exceeds the ratio set in
the M2O[1:0] bits, it is out of synchronization. Then if the REFEN bit is
‘1’, the Frame Processor will start to search for synchronization again.
Additionally, the Excessive CRC-6 Error also leads to out of ESF
synchronization. In this condition, both the REFEN bit being ‘1’ and the
REFCRCE bit being ‘1’ will allow the Frame Processor to search for
synchronization again. If the REFEN bit is ‘0’, no error can lead to
reframe except for manually setting. The manual reframe is executed by
a transition from ‘0’ to ‘1’ on the REFR bit. During out of synchronization
state, the error event detection is suspended.
Once resynchronized, if the new-found F bit position differs from the
previous one, the change of frame alignment event is generated. This
event is captured by the COFAI bit and is forwarded to the Performance
Monitor.
T1 Digital Multiplexer (DM) Format (T1 only)
In T1 DM format, three kinds of errors are detected:
Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 14). Each unmatched Ft bit leads to
an Ft bit error event. When 2 or more Ft bit errors are detected in a
6-basic-frame fixed window, the severely Ft bit error occurs. This
error event is captured by the SFEI bit.
F Bit Error: Each received F bit is compared with the expected one
(refer to Table 14). Each unmatched F bit leads to an F bit error
59
0
1 - 8
-
60
A2 (Alarm Bit)
1 - 7
B (bit 8)
61
1
1 - 8
-
62
S1 (Switch Bit)
1 - 8
-
63
0
1 - 8
-
64
S2 (Switch Bit)
1 - 8
-
65
1
1 - 8
-
66
S3 (Switch Bit)
1 - 7
C (bit 8)
67
0
1 - 8
-
68
S4 (Switch Bit)
1 - 8
-
69
1
1 - 8
-
70
1 (Spoiler Bit)
1 - 8
-
71
0
1 - 8
-
72
0
1 - 7
D (bit 8)
Table 15: The Structure of SLC-96 (Continued)
Frame No.
F-Bit (Frame Alignment) - Ft
The Bit In Each Channel
Frame No.
F-Bit (Frame Alignment) - Fs
The Bit In Each Channel
Data Bit
Signaling Bit
Data Bit
Signaling Bit
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