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| 型號(hào)： | IDT82P2284BBG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 350/363頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | TXRX T1/J1/E1 4CHAN 208-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類(lèi)型： | 收發(fā)器 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 1.8V, 3.3V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 208-BGA |
| 供應(yīng)商設(shè)備封裝： | 208-PBGA（17x17） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | 82P2284BBG8 |
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IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
87
February 25, 2008
3.18.2.1 Transmit Clock Master Mode
In the Transmit Clock Master mode, each link uses its own timing
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are per-
timeslot aligned with the data on the TSDn pin.
In the Transmit Clock Master mode, the data on the system interface
is clocked by the TSCKn. The active edge of the TSCKn used to update
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead.
In the Transmit Clock Master mode, the TSFSn can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit.
The Transmit Clock Master mode includes two sub-modes: Transmit
Clock Master Full E1 mode and Transmit Clock Master Fractional E1
mode.
Transmit Clock Master Full E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame are clocked in by the TSCKn.
Transmit Clock Master Fractional E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The TSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.18.2.2 Transmit Clock Slave Mode
In the Transmit Clock Slave mode, the timing signal on the TSCKn
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to ‘0’, each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to ‘1’ and all four links are in the Transmit Clock Slave mode, the
four links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-timeslot aligned with the data on the TSDn
pin.
In the Transmit Clock Slave mode, the data on the system interface
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The speed of the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
Mb/s) or double the data rate (4.096 Mb/s). If all four links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the four links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
In the Transmit Clock Slave mode, the TSFSn can indicate the Basic
frame, CRC Multi-frame and/or Signaling Multi-frame. The indications
are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit. If the pulse on the TSFSn pin is not an integer
multiple of 125
s, this detection will be indicated by the TCOFAI bit. If
the TCOFAE bit is enabled, an interrupt will be reported by the INT pin
when the TCOFAI bit is ‘1’.
3.18.2.3 Transmit Multiplexed Mode
In the Transmit Multiplexed mode, one multiplexed bus is used to
transmit the data to all four links. The data of Link 1 to Link 4 is byte-
interleaved input from the multiplexed bus 1. When the data on the
multiplexed bus is input to four links, the sequence of the data is
arranged by setting the timeslot offset. The data to different links from
one multiplexed bus must be shifted at a different timeslot offset to avoid
data mixing.
In the Transmit Multiplexed mode, the timing signal on the MTSCK
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to all four links. The signaling bits on the MTSIGA
(MTSIGB) pin are per-timeslot aligned with the corresponding data on
the MTSDA (MTSDB) pin.
In the Transmit Multiplexed mode, the data on the system interface is
clocked by the MTSCK. The active edge of the MTSCK used to sample
the pulse on the MTSFS is determined by the FE bit. The active edge of
the MTSCK used to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) is determined by the DE bit. The FE bit and the DE
bit of the four links should be set to the same value respectively. If the
FE bit and the DE bit are not equal, the pulse on the MTSFS is ahead.
The MTSCK can be selected by the CMS bit to be the same rate as the
data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MTSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) pins. The pulse on the MTSFS pin is always
sampled on its first active edge.
In the Transmit Multiplexed mode, the MTSFS can indicate the Basic
frame, CRC Multi-frame and/or Signaling Multi-frame of the first link. The
indications are selected by the FSTYP bit. The active polarity of the
MTSFS is selected by the FSINV bit. The FSTYP bit and the FSINV bit
of the four links should be set to the same value. If the pulse on the
MTSFS pin is not an integer multiple of 125
s, this detection will be
indicated by the TCOFAI bit. If the TCOFAE bit is enabled, an interrupt
will be reported by the INT pin when the TCOFAI bit is ‘1’.
3.18.2.4 Offset
Bit offset and timeslot offset are both supported in all the operating
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/
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