參數(shù)資料
型號: IDT82V2044EPFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 59/73頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 QUAD SHORT 128-TQFP
標準包裝: 15
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 82V2044EPFG
62
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
1.Relative to nominal frequency, MCLK= ± 100 ppm
2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions
(0.2UI displacement for E1 per ITU G.823).
3.For all digital outputs. C load = 15pF
Table-63 Transmitter and Receiver Timing Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
MCLK frequency
E1:
T1/J1:
2.048/49.152
1.544/37.056
MHz
MCLK tolerance
-100
100
ppm
MCLK duty cycle
30
70
%
Transmit path
TCLK frequency
E1:
T1/J1:
2.048
1.544
MHz
TCLK tolerance
-50
+50
ppm
TCLK Duty Cycle
10
90
%
t1
Transmit Data Setup Time
40
ns
t2
Transmit Data Hold Time
40
ns
Delay time of THZ low to driver high impedance
10
us
Delay time of TCLK low to driver high impedance
75
U.I.
Receive path
Clock recovery capture
range 1
E1
± 80
ppm
T1/J1
± 180
RCLK duty cycle 2
40
50
60
%
t4
RCLK pulse width 2
E1:
T1/J1:
457
607
488
648
519
689
ns
t5
RCLK pulse width low time
E1:
T1/J1:
203
259
244
324
285
389
ns
t6
RCLK pulse width high time
E1:
T1/J1:
203
259
244
324
285
389
ns
Rise/fall time 3
20
ns
t7
Receive Data Setup Time
E1:
T1/J1:
200
244
324
ns
t8
Receive Data Hold Time
E1:
T1/J1:
200
244
324
ns
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