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| 型號(hào)： | IDT82V2048BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 160-BGA |
| 標(biāo)準(zhǔn)包裝： | 14 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BGA |
| 供應(yīng)商設(shè)備封裝： | 160-PBGA（15x15） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048BBG |
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15
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
2.4.3
B8ZS/HDB3/AMI LINE CODE RULE
Selectable B8ZS/HDB3 and AMI line coding/decoding is provided
when the device is configured in single rail mode. B8ZS rules for T1 and
HDB3 rules for E1 are enabled by setting bit CODE in register GCF to ‘0’
or pulling pin CODE low. AMI rule is enabled by setting bit CODE in
register GCF to ‘1’ or pulling pin CODE high. The settings affect all eight
channels.
Individual line code rule selection for each channel, if needed, is
available by setting bit SINGn in register e-SING to ‘1’ (to activate bit
CODEn in register e-CODE) and programming bit CODEn to select line
code rules in the corresponding channel: ‘0’ for B8ZS/HDB3, while ‘1’ for
AMI. In this case, the value in bit CODE in register GCF or pin CODE for
global control is unaffected in the corresponding channel and only affect
in other channels.
In dual rail mode, the decoder/encoder are bypassed. Bit CODE in
register GCF, bit CODEn in register e-CODE and pin CODE are ignored.
The configuration of the line code rule is summarized in Table-5.
2.4.4
LOSS OF SIGNAL (LOS) DETECTION
The Loss of Signal Detector monitors the amplitude and density of
the received signal on receiver line before the transformer (measured on
port A, B shown in Figure-14). The loss condition is reported by pulling
pin LOSn high. At the same time, LOS alarm registers track LOS condi-
tion. When LOS is detected or cleared, an interrupt will generate if not
masked. In host mode, the detection supports the ANSI T1.231 for T1
mode, ITU G.775 and ETSI 300 233 for E1 mode. In hardware mode, it
supports the ITU G.775 and ANSI T1.231.
Table-6 summarizes the conditions of LOS in clock recovery mode.
During LOS, the RDPn/RDNn continue to output the sliced data
when bit AISE in register GCF is set to ‘0’ or output all ones as AIS
(alarm indication signal) when bit AISE is set to ‘1’. The RCLKn is
replaced by MCLK only if the bit AISE is set.
2.4.5
ALARM INDICATION SIGNAL (AIS) DETECTION
Alarm Indication Signal is available only in host mode with clock
recovery, as shown in Table-7.
2.4.6
ERROR DETECTION
The device can detect excessive zeros, bipolar violation and B8ZS/
host mode, the e-CZER and e-CODV are used to determine whether
excessive zeros and code violation are reported respectively. When the
device is configured in AMI decoding mode, only bipolar violation can be
reported.
The error detection is available only in single rail mode in which the
pin CVn/RDNn is used as error report output (CVn pin).
The configuration and report status of error detection are summa-
rized in Table-8.
Table-5 Configuration of the Line Code Rule
Hardware Mode
Host Mode
CODE
Line Code Rule
CODE in GCF
CODEn in e-CODE
SINGn in e-SING
Line Code Rule
Low
All channels in B8ZS/HDB3
00/1
0
All channels in B8ZS/HDB3
00
1
10/1
0
All channels in AMI
High
All channels in AMI
11
1
01
1
CHn in AMI
1
0
1
CHn in B8ZS/HDB3
Table-6 LOS Condition in Clock Recovery Mode
Standard
Signal on
LOSn
ANSI T1.231 for T1
G.775 for E1
ETSI 300 233 for E1
LOS
Detected
Continuous Intervals
175
32
2048 (1 ms)
High
Amplitude(1)
1. LOS levels at device (RTIPn, RRINGn) with all ones signal. For more detail regarding the LOS parameters, please refer to Receiver Characteristics on page 49.
below typical 200 mVp
LOS
Cleared
Density
12.5% (16 marks in a sliding 128-bit
period) with no more than 99 contin-
uous zeros
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
Low
Amplitude(1)
exceed typical 250 mVp
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