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參數(shù)資料
| 型號(hào)： | IDT82V2048EBB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 18/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 208-BGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BGA |
| 供應(yīng)商設(shè)備封裝： | 208-PBGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048EBB |
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25
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.5
LOS AND AIS DETECTION
3.5.1
LOS DETECTION
The Loss of Signal Detector monitors the amplitude of the incoming sig-
nal level and pulse density of the received signal on RTIPn and RRINGn.
LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0AH...). LOS will be
declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0,
0AH...). LOS status is cleared by pulling LOSn pin to low.
Figure-14 LOS Declare and Clear
LOS detect level threshold
With the Adaptive Equalizer off, the amplitude threshold Q is fixed on
800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hys-
teresis).
With the Adaptive Equalizer on, the value of Q can be selected by
LOS[4:0] bit (RCF1, 08H...), while P=Q+4 dB (4 dB is the LOS level detect
hysteresis). Refer to Table 34, “RCF1: Receiver Configuration Register 1,”
on page 43 for LOS[4:0] bit (RCF1, 08H...) values available.
Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT0, 0AH...) and T1E1 bit (GCF0, 40H).
both with and without the Adaptive Equalizer enabled.
All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
tion” at the RTIPn/RRINGn side and output recovery clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
the maximum receive sensitivity) when AISE bit (MAINT0, 0AH...) is 0; or
output All Ones as AIS when AISE bit (MAINT0, 0AH...) is 1. In this case
RCLKn output is replaced by MCLK.
On the line side, the TTIPn/TRINGn will output All Ones as AIS when
ATAO bit (MAINT0, 0AH...) is 1. The All Ones pattern uses MCLK as the
reference clock.
LOS indicator is always active for all kinds of loopback modes.
signal level<Q
(observing windows= N)
(observing windows= M)
signal level>P
density=OK
LOS=1
LOS=0
Table-13 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled
Control bit
LOS declare threshold
LOS clear threshold
T1E1
LAC
1=T1/J1
0=T1.231
Level < 800 mVpp
N=175 bits
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
1=I.431
Level < 800 mVpp
N=1544 bits
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
0=E1
0=G.775
Level < 800 mVpp
N=32 bits
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
1=I.431/ETSI
Level < 800 mVpp
N=2048 bits
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
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