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| 型號(hào)： | IDT82V2058DA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | OCTAL E1 SHORT HAUL LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 43/375頁(yè) |
| 文件大?。?/td> | 2430K |
| 代理商： | IDT82V2058DA |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
32
October 7, 2003
3.8.2.1.3
CAS Signaling Multi-Frame
After the Basic Frame has been synchronized, the Frame Proces-
sor starts to search for CAS Signaling Multi-Frame alignment signal if
the CASEN bit is ‘1’.
The Signaling Multi-Frame alignment pattern is located in the high
nibble (Bit 1 ~ Bit 4) of TS16. Its pattern is ‘0000’. When the pattern is
found in TS16 and the high nibble of the previous TS16 are not all zeros,
the Signaling Multi-Frame synchronization is acquired and it is indicated
with a ‘0’ in the OOSMFV bit. The frame containing the Signaling Multi-
Frame alignment pattern is Frame 0 of Signaling Multi-Frame. The TS16
structure of the Signaling Multi-Frame is shown in Figure 11. The entire
content in TS16 of Frame 0 of Signaling Multi-Frame is ‘0000XYXX’. ‘Y’
is for remote Signaling Multi-Frame alarm indication and ‘X’s are extra
bits. The codeword ‘ABCD’ are the signaling bits for different timeslots.
Figure 11. TS16 Structure Of CAS Signaling Multi-
Frame
3.8.2.2
Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor keeps
on monitoring the received data stream to detect errors and judge if it is
out of synchronization.
The following ten kinds of errors are detected:
1. FAS/NFAS Bit/Pattern Error: The criteria of this error are deter-
mined by the WORDERR bit and the CNTNFAS bit (refer to Table 19).
This error event is captured by the FERI bit and is forwarded to the Per-
formance Monitor.
2. CRC Multi-Frame Alignment Pattern Error: The received CRC
Multi-Frame alignment signals are compared with the expected ones
(‘001011’). When one or more bits do not match, a single CRC Multi-
Frame alignment pattern error event is generated. This error event is
captured by the CMFERI bit.
3. CRC-4 Error: When the local calculated CRC-4 of the current
received CRC Sub Multi-Frame does not match the received CRC-4 of
the next received CRC Sub Multi-Frame, a single CRC-4 error event is
generated. This error event is captured by the CRCEI bit and is for-
warded to the Performance Monitor.
4. Excessive CRC-4 Error: Once the accumulated CRC-4 errors
are not less than 915 occasions (915 is included) in a 1 second fixed
window, an excessive CRC-4 error event is generated. This error event
is captured by the EXCRCERI bit.
5. CAS Signaling Multi-Frame Alignment Pattern Error: The
received Signaling Multi-Frame alignment signals are compared with the
expected ones (‘0000’). When one or more bits do not match, a single
CAS Signaling Multi-Frame alignment pattern error event is generated.
This error event is captured by the SMFERI bit.
6. Far End Block Error (FEBE): When any of the CRC error indica-
tion (E1 or E2) bits is received as a logic 0, a far end block error event is
generated. This error event is captured by the FEBEI bit and is for-
warded to the Performance Monitor.
7. Continuous RAI & FEBE Error: When a logic 1 is received in the
A bit and a logic 0 is received in any of the E1 or E2 bit for 10 ms, the
RAICRCV bit is set. This bit is cleared if any of the conditions is not met.
8. Continuous FEBE Error: When a logic 0 is received in any of the
E1 or E2 bits on
≥
990 occasions per second for the latest 5 consecutive
seconds, the CFEBEV bit is set, otherwise this bit will be cleared.
9. NT FEBE Error (per ETS 300 233): If the 4-bit Sa6 codeword of a
CRC Sub Multi-Frame is matched with ‘0001’ or ‘0011’, the Network Ter-
minal Far End Block Error event is generated. This error event is cap-
tured by the TFEBEI bit and is forwarded to the Performance Monitor.
A
B
C
D
A
B
C
D
for TS31
for TS15
A
B
C
D
A
B
C
D
for TS18
for TS2
A
B
C
D
A
B
C
D
for TS17
for TS1
F1
F2
F15
0
0
0
0
X0
Y
X1
X2
F0
Signaling Multi-Frame
alignment pattern
RMAI
Extra Bits
TS16 (Bit 1 - Bit 8)
Table 19: FAS/NFAS Bit/Pattern Error Criteria
WORDERR CNTNFAS
Error Generation
0
1
0
0
0
1
Each bit error in FAS is counted as an error event.
A FAS pattern error is counted as an error event.
Each bit error in FAS or NFAS error is counted as an
error event.
A FAS pattern error or NFAS error is counted as an
error event.
1
1
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| IDT82V2058DABLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:OCTAL E1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2058DAG | 功能描述:IC LIU E1 8CH SHORT HAUL 144TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2058DAGBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:OCTAL E1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2058LBB | 功能描述:IC LIU E1 8CH SHORT HAUL 160-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2058LBBG | 功能描述:IC LIU E1 8CH SHORT HAUL 160-BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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