參數(shù)資料
型號(hào): IDT82V2084PFG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 31/75頁(yè)
文件大小: 0K
描述: IC LIU T1/J1/E1 4CH 128-TQFP
標(biāo)準(zhǔn)包裝: 15
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 82V2084PFG
37
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.2
JITTER ATTENUATION CONTROL REGISTER
Table-28 GCF1: Global Configuration Register 1
(R/W, Address = 60H)
Symbol
Bit
Default
Description
MON[3:0]
7-4
0000
MON selects the transmitter or receiver channel to be monitored.
= 0000: receiver 1 is in normal operation without monitoring
= 0001: reserved
= 0010: monitor receiver 2
= 0011: reserved
= 0100: monitor receiver 3
= 0101: reserved
= 0110: monitor receiver 4
= 0111: reserved
= 1000: transmitter 1 is in normal operation without monitoring
= 1001: reserved
= 1010: monitor transmitter 2
= 1011: reserved
= 1100: monitor transmitter 3
= 1101: reserved
= 1110: monitor transmitter 4
= 1111: reserved
-
3-0
0000
Reserved
Table-29 INTCH: Interrupt Channel Indication Register
(R, Address = 80H)
Symbol
Bit
Default
Description
INT_CH[7:0]
7-0
00H
INT_CH[0, 2, 4 or 6]=1 indicates that an interrupt was generated by channel 1, 2, 3 or 4 respectively.
Table-30 JACF: Jitter Attenuator Configuration Register
(R/W, Address = 01H,41H,81H,C1H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved
JA_LIMIT
5
0
Wide Jitter Attenuation bandwidth
= 0: normal mode
= 1: JA limit mode
JACF[1:0]
4-3
00
Jitter Attenuator configuration
= 00/10: JA not used
= 01: JA in transmit path
= 11: JA in receive path
JADP[1:0]
2-1
00
Jitter Attenuator depth selection
= 00: 128 bits
= 01: 64 bits
= 10/11: 32 bits
JABW
0
Jitter transfer function bandwidth selection
JABW
T1/J1
E1
05 Hz
6.8 Hz
1
1.25 Hz
0.9 Hz
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