參數(shù)資料
型號： IDT82V3255DK
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： TQFP-64
文件頁數(shù)： 4/127頁
文件大小： 868K
代理商： IDT82V3255DK
Table of Contents
4
June 19, 2006
IDT82V3255
WAN PLL
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 31
3.10.1.5 Holdover Mode ................................................................................................................................................................. 31
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32
3.10.1.5.4 Manual ........................................................................................................................................................... 32
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 32
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 32
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 32
3.10.2.2 Locked Mode .................................................................................................................................................................... 32
3.10.2.3 Holdover Mode ................................................................................................................................................................. 32
3.11 T0 / T4 DPLL OUTPUT .................................................................................................................................................................................34
3.11.1 PFD Output Limit ............................................................................................................................................................................ 34
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 34
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 34
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 34
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 34
3.11.5.1 T0 Path ............................................................................................................................................................................. 34
3.11.5.2 T4 Path ............................................................................................................................................................................. 35
3.12 T0 / T4 APLL .................................................................................................................................................................................................36
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ...........................................................................................................................................36
3.13.1 Output Clocks ................................................................................................................................................................................. 36
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 38
3.14 INTERRUPT SUMMARY ...............................................................................................................................................................................40
3.15 T0 AND T4 SUMMARY .................................................................................................................................................................................40
3.16 POWER SUPPLY FILTERING TECHNIQUES .............................................................................................................................................41
3.17 LINE CARD APPLICATION ..........................................................................................................................................................................42
4 MICROPROCESSOR INTERFACE ..................................................................................................................................43
5 JTAG ................................................................................................................................................................................45
6 PROGRAMMING INFORMATION ....................................................................................................................................46
6.1
REGISTER MAP ............................................................................................................................................................................................46
6.2
REGISTER DESCRIPTION ...........................................................................................................................................................................51
6.2.1
Global Control Registers ............................................................................................................................................................... 51
6.2.2
Interrupt Registers ......................................................................................................................................................................... 58
6.2.3
Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 62
6.2.4
Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 73
6.2.5
T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 84
6.2.6
T0 / T4 DPLL State Machine Control Registers ........................................................................................................................... 88
6.2.7
T0 / T4 DPLL & APLL Configuration Registers ............................................................................................................................ 90
6.2.8
Output Configuration Registers .................................................................................................................................................. 103
6.2.9
PBO & Phase Offset Control Registers ...................................................................................................................................... 107
6.2.10 Synchronization Configuration Registers ................................................................................................................................. 109
7 THERMAL MANAGEMENT ...........................................................................................................................................111
7.1
JUNCTION TEMPERATURE ......................................................................................................................................................................111
7.2
EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ...................................................................................................................111
7.3
HEATSINK EVALUATION ..........................................................................................................................................................................111
8 ELECTRICAL SPECIFICATIONS ..................................................................................................................................112
8.1
ABSOLUTE MAXIMUM RATING ................................................................................................................................................................112
8.2
RECOMMENDED OPERATION CONDITIONS ..........................................................................................................................................112
8.3
I/O SPECIFICATIONS .................................................................................................................................................................................113
8.3.1
CMOS Input / Output Port ............................................................................................................................................................ 113
8.3.2
PECL / LVDS Input / Output Port ................................................................................................................................................ 114
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IDT82V3255DKG 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
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IDT82V3255EDGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TFBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
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