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參數(shù)資料
| 型號： | IDTCSPF2510CPGGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 3.3鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 68K |
| 代理商： | IDTCSPF2510CPGGI |
3
IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0oC TO 85oC TEMPERATURE RANGE
STATIC FUNCTION TABLE
(AV
DD
= 0V)
DY NAMIC FUNCTION TABLE
(AV
DD
= 3.3V)
PIN DESCRIPTION
Terminal
Name
No.
CLK
24
Type
I
Description
Clock input. CLK provides the clock signal to be distributed by the CSPF2510C clock driver. CLK is used to provide the reference
signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain
phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is nomnally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When
G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25
series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be
disabled to a logic-low state by de-asserting the G control input. Each output has an integrated 25
series-damping resistor.
FBIN
13
I
G
11
I
FBOUT
12
O
Y (0:9)
3, 4, 5, 8, 9,
15, 16, 17,
20, 21
23
O
AV
DD
Power
Analog power supply. AV
DD
provides the power reference for the analog circuitry. In addition, AV
DD
can be used to bypass the PLL
for test purposes. When AV
DD
is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
Ground
AGND
V
DD
GND
1
Ground
2, 10, 14, 22 Power
6, 7, 18, 19 Ground
Inputs
Outputs
G
L
L
H
H
H
CLK
L
H
H
L
running
Y (0:9)
L
L
H
L
running
FBOUT
L
H
H
L
running
Inputs
Outputs
G
X
L
CLK
L
running
Y (0:9)
L
L
FBOUT
L
running in
phase with CLK
H
running in
phase with CLK
H
L
H
H
L
running
running in
phase with CLK
H
H
H
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPF2510CPGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPT855PG | 功能描述:IC PLL CLK DRIVER 2.5V 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT855-PG | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 60MHz to 220MHz 28-Pin TSSOP Tube |
| IDTCSPT855PG8 | 功能描述:IC PLL CLK DRIVER 2.5V 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT855PGG | 功能描述:IC PLL CLK DRIVER 2.5V 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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