參數(shù)資料
型號(hào): IDTIDT71P79104250BQI
廠商: Integrated Device Technology, Inc.
英文描述: 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
中文描述: 35.7流水線⑩二二氧化硅的DDR SRAM的爆裂2
文件頁(yè)數(shù): 9/23頁(yè)
文件大?。?/td> 641K
代理商: IDTIDT71P79104250BQI
6.42
9
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1) (2)
Capacitance
(TA = +25°C, f = 1.0MHz)
(1)
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximumrating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed VDD during normal operation.
Note:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
DD
= 1.8V
V
DDQ
= 1.5V
5
pF
C
CLK
Clock Input Capacitance
6
pF
C
O
Output Capacitance
7
pF
6432 tbl 06
Symbol
Rating
Value
Unit
V
TERM
Supply Voltage on V
DD
wth
Respect to GND
–0.5 to +2.9
V
V
TERM
Supply Voltage on V
DDQ
wth
Respect to GND
–0.5 to V
DD
+0.3
V
V
TERM
Voltage on Input termnals with
respect to GND
–0.5 to V
DD
+0.3
V
V
TERM
Voltage on output and I/O
termnals wth respect to GND
–0.5 to V
DDQ
+0.3
T
BIAS
Temperature Under Bias
–55 to +125
°C
T
STG
Storage Temperature
–65 to +150
°C
I
OUT
Continuous Current into Outputs
+ 20
mA
6432 tbl 05
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Power Supply Voltage
1.7
1.8
1.9
V
V
DDQ
I/O Supply Voltage
1.4
1.5
1.9
V
V
SS
Ground
0
0
0
V
V
REF
Input Reference Voltage
-
V
DDQ/2
-
V
T
A
Ambient
Temperature
(1)
Commercial
0 to +70
o
c
Industrial
-40 to +85
o
c
6432 tbl 04
Notes:
1) All byte write (
BW
x) a
nd nibble write
(
NW
x) signals are sampled on
the rising edge of K and again on
K
. The data that is present on the data bus\
in the designated byte/nibble will be latched into the input if the corresponding
BW
x or
NW
x is held low. The rising edge of K will sample the first byte/nibble
of the two word burst and the rising edge of
K
will sample the second byte
nibble of the two word burst.
2) The availability of the
BW
x or
NW
x on designated devices is described in the
pin description table.
3) The DDRII SIO Burst of two SRAMhas data forwarding. A read request that
is initiated on cycle following a write request to the same address will produce
the newly written data in response to the read request.
Signal
BW
0
BW
1
BW
2
BW
3
NW
0
NW
1
Write Byte 0
L
X
X
X
X
X
Write Byte 1
X
L
X
X
X
X
Write Byte 2
X
X
L
X
X
X
Write Byte 3
X
X
X
L
X
X
Write Nibble 0
X
X
X
X
L
X
Write Nibble 1
X
X
X
X
X
L
6432 tbl 09
Write Descriptions
(1,2)
Note:
1. During production testing, the case temperature equals the ambient
temperature.
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IDTIDT71P79104267BQ 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104267BQI 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79204167BQ 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79204167BQI 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
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