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參數(shù)資料
| 型號： | IDTIDT71P79604200BQI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| 中文描述： | 35.7流水線⑩二二氧化硅的DDR SRAM的爆裂2 |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 641K |
| 代理商： | IDTIDT71P79604200BQI |
6.42
3
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Pin Definitions
Symbol
Pin Function
Description
D[X:0]
Input
Synchronous
Data input signals, sampled on the rising edge of K and
K
clocks during valid write operations
2Mx 8 -- D[7:0]
2Mx 9 -- D[8:0]
1Mx 18 -- D[17:0]
512K x 36 -- D[35:0]
BW
0
,
BW
1
BW
2
,
BW
3
Input
Synchronous
Byte Write Select 0, 1, 2, and 3 are active LOW Sampled on the rising edge of the K and again on the rising
edge of
K
clocks during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same
edge as the data. Deselecting a Byte Write Select wll cause the corresponding byte of data to be ignored and
not written in to the device.
2Mx 9 --
BW
0
controls DQ[8:0]
1Mx 18 --
BW
0
controls DQ[8:0] and
BW
1
controls DQ[17:9]
512K x 36 --
BW
0
controls DQ[8:0],
BW
1
controls DQ[17:9],
BW
2
controls DQ[26:18] and
BW
3
controls DQ[35:27]
NW
0
NW
1
Input
Synchronous
Nibble Write Select 0 and 1 are active LOW Available only on x8 bit parts instead of Byte Write Selects.
Sampled on the rising edge of the K and
K
clocks during write operations. Used to select which nibble is written
into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the
nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select wll cause the
corresponding nibble of data to be ignored and not written in to the device.
2Mx 8--
NW
0 controls D[3:0] and
NW
1 controls D[7:4]
SA
Input
Synchronous
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
Q[X:0]
Output
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on
the rising edge of both the C and
C
clocks during Read operations or K and
K
when operating in single clock
mode. When the Read port is deselect ed, Q[X:0] are automatically three-stated.
LD
Input
Synchronous
Load Control Logic. Sampled on the rising edge of K. If
LD
is low a two word burst read or write operation wll
be initiated as designated by the R/
W
input. If
LD
is high during the rising edge of K, operations in progress will
complete, but newoperations wll not be initiated.
R/
W
Input
Synchronous
Read or Write Control Logic. If
LD
is lowduring the rising edge of K, the R/
W
indicates whether a newoperation
should be a read or write. If R/
W
is high, a read operation wll be initiated, if R/
W
is low a write operation will be
initiated. If the
LD
input is high during the rising edge of K, the R/
W
input wll be ignored.
C
Input Clock
Positive Output Clock Input. C is used in conjunction wth
C
to clock out the Read data fromthe device. C and
C
can be used together to deskewthe flight times of various devices on the board back to the controller See
application example for further details.
C
Input Clock
Negative Output Clock Input.
C
is used in conjunction wth C to clock out the Read data fromthe device. C and
C
can be used together to deskewthe flight times of various devices on the board back to the controller See
application example for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive
out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input.
K
is used to capture synchronous inputs being presented to the device and to drive
out data through Q[X:0] when in single clock mode.
CQ,
CQ
Output Clock
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data
outputs and can be used as a data valid indication. These signals are free running and do not stop when the
output data is three stated.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the systemdata bus
impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and
ground. Alternately, this pin can be connected directly to V
DDQ
, which enables the mnimumimpedance mode.
This pin cannot be connected directly to GND or left unconnected.
6432 tbl 02a
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| IDTIDT71P79604250BQ | 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79604250BQI | 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDTIDT71P79604250BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79604250BQI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79604267BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79604267BQI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| IDTIDT71P79804167BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
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