參數(shù)資料
型號: IDTQS34XST253Q38
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 編、解碼器及復(fù)用、解復(fù)用
英文描述: OCTAL 1 LINE TO 4 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO80
封裝: 0.150 INCH, MILLIPAK, DIP-80
文件頁數(shù): 10/10頁
文件大?。?/td> 128K
代理商: IDTQS34XST253Q38
9
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
IBH
+500
Sinking
Current
( + )
IBHL
IBH
IBHH
+60
+20
– 60
– 20
+60 IBHL
0.8V
2V
VIH
– 60 IBHL
V IL
Sourcing
Current
( – )
IBH
– 500
Vcc
+20 IBH
– 20 IBH
Voltage
VT
V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT
VT
≡≡≡≡≡ Threshold Voltage ≈ 1.5V
VIL
≈ .8
VIH
≈ 2V
ACTIVE TERMINATOR OR BUS-HOLD CIRCUIT
The Active Terminator circuit, also known as the bus-hold circuit, is configured as a “weak latch” with positive feedback. When connected to a
TTL or CMOS input port, the bus-hold circuit holds the last logic state at the input when the input is “disconnected” from the driver. When the output
of a device connected to such an input attempts a logic level transition, it will overdrive the bus-hold circuit. The primary benefit of a bus-hold circuit
is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power
dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to Vcc or GND to prevent bus floating, because
the bus-hold circuit does not consume any static power.
This figure shows the input V-I characteristics of a typical bus-hold implementation. The input characteristics resemble a resistor. As the input
voltage is increased from 0 volts, the input “sink” current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the
latch changes the logic state due to positive feedback and the direction of the current is reversed. As the input voltage is further increased towards
Vcc, the input “source” current begins to decrease, reaching the lowest level at VIN = Vcc.
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