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參數(shù)資料
| 型號： | IDTQS5LV919-55Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 106K |
| 代理商： | IDTQS5LV919-55Q |
9
INDUSTRIALTEMPERATURERANGE
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
CM MU
CMMU
CPU
CMMU
CM MU
CMMU
CM MU
CMMU
CPU
CMMU
CM MU
CMMU
PLL
2f
PLL
2f
CPU
CARD
CPU
CARD
CLOCK
@f
SYS TEM
CLO CK
SO URCE
QS5LV919
DISTRIBUTE
CLO CK @ f
CLOCK @ 2f
at point of use
MEMORY
CO NTROL
PLL
2f
ME MO RY
CAR DS
CLO CK @ 2f
at point of use
QS5LV919
Figure 3. Multiprocessing Application Using the QS5LV919 for Frequency Multiplication and Low Board-to-Board skew
QS5LV919 System Level Testing Functionality
When the PLL_EN pin is LOW, the PLL is bypassed and the QS5LV919 is
in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q
output is inverted from the selected SYNC input, and the Q outputs are divide-
by-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divide-
by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-
by-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A recommended test
configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie
PLL_EN and REF_SEL together and connect them to the test select logic.
This functionality is needed since most board-level testers run at 1 MHz or
below, and the QS5LV919 cannot lock onto that low of an input frequency. In
the test mode described above, any test frequency test can be used.
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