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參數(shù)資料
| 型號(hào)： | IMIC9630 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | IMIC9630 |
PCIX I/O System Clock Generator with EMI
Control Features
C9530
Cypress Semiconductor Corporation
Document #: 38-07033 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised May 9, 2003
Features
Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
Input clock frequency of 25 MHz to 33.3 MHz
Output frequencies of XINx1, XINx2, XINx3 and XINx4
Output grouped in two banks of five clocks each
One REF XIN clock output
SMBus clock control interface for individual clock
disabling and SSCG control and individual back
frequency selection
Output clock duty cycle is 50% (± 5%)
< 250 ps skew between output clocks within a bank
Output jitter < 250 psec (175 psec with all outputs at the
same frequency)
Spread Spectrum feature for reduced electromagnetic
interference (EMI)
OE pins for entire output bank enable control and
testability
48-pin SSOP and TSSOP packages
Table 1. Test Mode Logic Table
[1]
Note:
1.
A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state
REF.
Input Pins
SA1
SB1
LOW
LOW
HIGH
HIGH
X
Output Pins
CLKA
CLKB
XIN
2 * XIN
3 * XIN
4 * XIN
Three-state
OEA
OEB
HIGH
HIGH
HIGH
HIGH
LOW
SA0
SB0
LOW
HIGH
LOW
HIGH
X
REF
XIN
XIN
XIN
XIN
Three-state
Block Diagram
Pin Configuration
XIN
CLKB4
OEB
BGOOD#
REF
CLKB3
CLKB2
CLKB1
CLKB0
CLKA3
CLKA4
OEA
CLKA2
CLKA1
CLKA0
/N
SSCG#
SSCG
Logic
/N
1
0
1
0
XOUT
I
2
C
Control
Logic
SCLK
IA(0:2)
SA(0,1)
SB(0,1)
AGOOD#
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XIN
VDD
XOUT
VSS
SA1
VSS
CLKA0
VDDA
CLKA2
VSS
VDDA
CLKA4
VSS
CLKA1
AGOOD#
VSS
IA0
IA1
IA2
AVDD
OEA
OEB
VSS
SSCG#
VSS
AVDD
BGOOD#
AVDD
CLKB4
VDDB
VSS
VDDB
CLKB2
CLKB1
VSS
SB1
VSS
CLKB3
CLKB0
SB0
VDD
VSS
VDD
SCLK
SDATA
C
REF
41
42
43
44
45
46
47
48
SA0
CLKA3
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