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參數(shù)資料
| 型號(hào)： | IMS82C55AZ96 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Programmable Peripheral Interface |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PQCC44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-018AC, LCC-44 |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大?。?/td> | 502K |
| 代理商： | IMS82C55AZ96 |
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9
FN6140.1
June 28, 2005
Operating Modes
Mode 1
- (Strobed Input/Output). This functional configuration
provides a means for transferring I/O data to or from a specified
port in conjunction with strobes or “hand shaking” signals. In
mode 1, port A and port B use the lines on port C to generate or
accept these “hand shaking” signals.
Mode 1 Basic Function Definitions:
Two Groups (Group A and Group B)
Each group contains one 8-bit port and one 4-bit control/data
port
The 8-bit data port can be either input or output. Both inputs
and outputs are latched.
The 4-bit port is used for control and status of the 8-bit port.
Input Control Signal Definition
(Figures 6 and 7)
STB (Strobe Input)
A “l(fā)ow” on this input loads data into the input latch.
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been loaded
into the input latch: in essence, an acknowledgment. IBF is set
by STB input being low and is reset by the rising edge of the
RD input.
INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU when
an input device is requesting service. INTR is set by the
condition: STB is a “one”, IBF is a “one” and INTE is a “one”. It
is reset by the falling edge of RD. This procedure allows an
input device to request service from the CPU by simply strobing
its data into the port.
INTE A
Controlled by bit set/reset of PC4.
INTE B
Controlled by bit set/reset of PC2.
Output Control Signal Definition
(Figure 8 and 9)
OBF
- (Output Buffer Full F/F). The OBF output will go “l(fā)ow”
to indicate that the CPU has written data out to the specified
port. This does not mean valid data is sent out of the port at this
time since OBF can go true before data is available. Data is
guaranteed valid at the rising edge of OBF, (See Note 1). The
OBF F/F will be set by the rising edge of the WR input and reset
by ACK input being low.
FIGURE 6. MODE 1 INPUT
FIGURE 7. MODE 1 (STROBED INPUT)
1
D7
0
D6
1
D5
1
D4
1/0
D3 D2 D1 D0
CONTROL WORD
MODE 1 (PORT A)
PC4
8
IBFA
PC5
INTE
A
PA7-PA0
STBA
INTRA
PC3
PC6, PC7
I/O
2
RD
PC6, PC7
1 = INPUT
0 = OUTPUT
1
D7 D6 D5 D4 D3 D2 D1 D0
CONTROL WORD
MODE 1 (PORT B)
PC2
8
IBFB
PC1
INTE
B
PB7-PB0
STBB
INTRB
PC0
RD
1
1
tST
STB
INTR
RD
INPUT FROM
PERIPHERAL
IBF
tSIB
tSIT
tPH
tPS
tRIT
tRIB
MS82C55A, MQ82C55A
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