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參數(shù)資料
| 型號(hào)： | IMS82C55AZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Programmable Peripheral Interface |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PQCC44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-018AC, LCC-44 |
| 文件頁(yè)數(shù)： | 2/24頁(yè) |
| 文件大?。?/td> | 502K |
| 代理商： | IMS82C55AZ |
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2
FN6140.1
June 28, 2005
Pinouts
MS82C55A (PLCC)
TOP VIEW
MQ82C55A (MQFP)
TOP VIEW
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
P
P
P
P
P
P
P
P
P
N
NC
D4
D5
D6
D7
V
CC
RESET
D0
D1
D2
D3
R
P
P
P
P
P
P
P
P
W
N
P
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
26
25
24
23
22
21
20
19
18
7
8
9
10
11
12
13
14
15
16
17
PC6
PC7
A0
A1
GND
CS
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
PC5
PC4
PC0
PC1
PC2
28
27
26
25
24
23
22
21
20
19
18
PB7
V
CC
D7
D6
D5
D4
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
N
P
P
P
P
W
RESET
D0
D1
D2
D3
R
P
P
P
P
N
P
P
P
P
N
N
P
P
P
P
Pin Description
SYMBOL
TYPE
DESCRIPTION
V
CC
V
CC
: The +5V power supply pin. A 0.1
μ
F capacitor between V
CC
and GND is recommended for decoupling.
GND
GROUND
D0-D7
I/O
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET
I
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode.
CS
I
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
RD
I
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WR
I
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
A0-A1
I
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PA0-PA7
I/O
PORT A: 8-bit input and output port.
PB0-PB7
I/O
PORT B: 8-bit input and output port.
PC0-PC7
I/O
PORT C: 8-bit input and output port.
MS82C55A, MQ82C55A
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