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參數(shù)資料
| 型號(hào)： | IMST425-G20M |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁(yè)數(shù)： | 4/74頁(yè) |
| 文件大小： | 563K |
| 代理商： | IMST425-G20M |
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IMS T400
/ 74
4
The IMS T400 can directly access a linearaddress space of 4 Gbytes. The 32 bit wide memory interface
uses multiplexeddata and addresslines andprovides adata rate ofupto 4 bytes every150 nanoseconds
(26.6 Mbytes/sec)for a 20 MHz device. Aconfigurable memory controller provides all timing, control and
DRAM refresh signals for a wide variety of mixed memory systems.
System Services include processor reset and bootstrap control, together with facilities for error analysis.
Error signals may be daisy-chained in multi-transputer systems.
The standard INMOS communicationlinks allownetworks oftransputer familyproductsto be constructed
by directpoint topoint connectionswithno externallogic.TheIMS T400links supportthestandardoperat-
ing speedof10 Mbits/sec,but alsooperate at 5or 20Mbits/sec. Eachlinkcantransferdatabi-directionally
at up to 2.35 Mbytes/sec.
The IMS T400-20 is pin compatible with the IMS T805-20 and IMS T425-20 and can be plugged directly
into a circuit designed for those devices.
The transputer is designed to efficiently implement high level languages such as ANSI C and
occam
.
Access to the transputer at machine level is seldom required, but if necessaryrefer to the TransputerIn-
struction Set – A Compiler Writer’s Guide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IMST425G20S | Peripheral IC |
| IMST425-G20S | 32-Bit Microprocessor |
| IMST425G25S | Peripheral IC |
| IMST425-G25S | 32-Bit Microprocessor |
| IMST425G30S | Peripheral IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IMST425G20S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| IMST425-G20S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| IMST425G25S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| IMST425-G25S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| IMST425G30S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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