參數(shù)資料
型號(hào)： IMST425-G20S
元件分類(lèi)： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 15/74頁(yè)
文件大?。?/td> 563K
代理商： IMST425-G20S
5 External memory interface
/ 74
15
5.1
Pin functions
5.1.1
MemAD2–31
External memoryaddresses anddata are multiplexedonone bus. Onlythetop 30bitsof addressare out-
put on the external memory interface, using pins
MemAD2-31
. They are normally output only during
Tstates T1
and
T2
, and should be latched during this time. The data bus is 32 bits wide. It uses
Me-
mAD2-31
for the top 30 bits and
MemnotRfD1
and
MemnotWrD0
for the lower two bits.
5.1.2
notMemRd
For a read cycle the read strobe
notMemRd
is low during
T4
and
T5
. Data is read by the transputer on
the rising edge of this strobe, and may beremoved immediately afterward. Ifthe strobeduration is insuffi-
cient it may be extended by adding extra periods
Tm
to either or both of the
Tstates T4
and
T5
. Further
extension may be obtained by inserting wait states at the end of
T4
.
5.1.3
MemnotWrD0
During
T1
and
T2
this pin will be low if the cycle is a writecycle, otherwise it will be high. During
Tstates
T3
to
T6
it becomes bit 0 of the data bus. In both cases it follows the general timing of
MemAD2-31
.
5.1.4
notMemWrB0–3
Because the transputer uses word addressing, four write strobes are provided; one to write each byte of
the word.
notMemWrB0
addresses the least significant byte.
5.1.5
notMemS0–4
Tofacilitate controlof differenttypes of memoryand devices, theEMI is providedwith five strobe outputs,
four of whichcanbe configured bytheuser.The strobesare conventionallyassignedthe functions shown
in the read and write cycle diagrams, although there is no compulsion to retain these designations.
5.1.6
MemWait
Waitstates can be selected by taking
MemWait
high. Externally generated wait states can be added to
extend the duration of
T4
indefinitely.
5.1.7
MemnotRfD1
During
T1
and
T2
, this pin is lowif the address on
MemAD2-31
is a refresh address, otherwise it is high.
During
Tstates T3
to
T6
it becomesbit 1 of the data bus.In bothcases it followsthe general timing of
Me-
mAD2-31
.
5.1.8
notMemRf
The IMS T400 can be operated with memory refresh enabled or disabled. The selection is made during
memory configuration, when the refresh interval is also determined.
5.1.9
RefreshPending
When high, this pin signals that a refresh cycle is pending.
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