參數(shù)資料
型號(hào)： IMST425-G25S
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁數(shù)： 12/74頁
文件大?。?/td> 563K
代理商： IMST425-G25S
IMS T400
/ 74
12
4
Memory
The IMS T400 has 2 Kbytes of fast internal static memory for high ratesof data throughput.Each internal
memory access takes one processor cycle
ProcClockOut
(page 16). The transputer can also access
4 Gbytes of external memory space. Internal and external memory are part of the same linear address
space. Internal RAM can be disabled by holding
DisableIntRAM
high. All internal addresses are then
mapped to external RAM. This pin should not be altered after
Reset
has been taken low.
IMS T400 memory is byte addressed, with words aligned on four-byte boundaries. The least significant
byte of a word is the lowest addressed byte.
The bitsinabyteare numbered 0 to 7,with bit 0 theleastsignificant. The bytes are numberedfrom 0, with
byte 0 the least significant. In general, wherever a value is treatedas a numberof component values, the
components arenumberedin order ofincreasingnumerical significance,with theleastsignificant compo-
nent numbered 0. Where values are stored inmemory, the least significantcomponent value is stored at
the lowest (most negative) address.
Internalmemorystartsatthemost negativeaddress#80000000andextendsto#800007FF Usermemory
begins at #80000070; this location isgiven thenameMemStart. An instruction ldmemstartvalis provided
to obtain the value of
MemStart
.
The context of a process in the transputer model involves a workspace descriptor (
WPtr
) and an instruc-
tionpointer(
IPtr
).
WPtr
isawordaddresspointertoaworkspaceinmemory.
IPtr
pointsto thenextinstruc-
tion tobe executedforthe processwhichis thecurrentlyexecuting process.Thecontextswitch performed
by the breakpoint instruction swaps the
WPtr
and
IPtr
of the currently executing process with the
WPtr
and
IPtr
held above
MemStart
. Twocontexts are held above
MemStart
, one for high priority and one for
low priority; this allows processes at both levels to have breakpoints. Note that on bootstrapping from a
link, these contexts are overwritten by the loaded code. If this is not acceptable, the values should be
peeked from memory before bootstrapping from a link.
The reserved area of internal memory below
MemStart
is used to implement link and event channels.
Twowords of memory are reserved for timer use, TPtrLoc0 for high priority processes and TPtrLoc1 for
low priority processes. They eitherindicate the relevant priority timer is not in use or point to the first pro-
cess on the timer queue at that priority level.
Valuesof certainprocessorregistersforthecurrentlow priorityprocessare savedinthereservedIntSave-
Loclocations when a high priority process pre-empts a low priority one. Other locations are reserved for
extended features such as block moves.
External memoryspace startsat #80000800and extendsup through #00000000to #7FFFFFFF.Memory
configuration data and ROM bootstrapping code must be in the most positive address space, starting at
#7FFFFF6C and #7FFFFFFE respectively.Address spaceimmediately below thisis conventionallyused
for ROM based code.
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