![](http://datasheet.mmic.net.cn/230000/IMST400_datasheet_15584548/IMST400_70.png)
IMS T400
/ 74
70
Operation
Code
13
4D
29
Memory
Code
21F3
24FD
22F9
Mnemonic
Processor
Cycles
2
3
2
3
1
2
1
1
2
Name
DEF
csub0
ccnt1
testerr
check subscript from 0
check count from 1
test error false and clear (no error)
test error false and clear (error)
set error
stop on error (no error)
clear halt–on–error
set halt–on–error
test halt–on–error
E
E
10
55
57
58
59
21F0
25F5
25F7
25F8
25F9
seterr
stoperr
clrhalterr
sethalterr
testhalterr
E
D
Table11.19
Error handling operation codes
Operation
Code
0
Memory
Code
00
Mnemonic
Processor
Cycles
3
11
13
9
11
1
1
2
1
1
6
6
Name
DEF
jump 0
jump 0 (break not enabled)
jump 0 (break enabled, high priority)
jump 0 (break enabled, low priority)
break (high priority)
break (low priority)
clear jump 0 break enable flag
set jump 0 break enable flag
test jump 0 break enable flag set
disable high priority timer interrupt
disable low priority timer interrupt
enable high priority timer interrupt
enable low priority timer interrupt
D
B1
2BF1
break
B2
B3
B4
7A
7B
7C
7D
2BF2
2BF3
2BF4
27FA
27FB
27FC
27FD
clrj0break
setj0break
testj0break
timerdisableh
timerdisablel
timerenableh
timerenablel
Table11.20
Debugger support codes
Operation
Code
5B
5C
5D
5E
does not apply to IMS T225
Memory
Code
25FB
25FC
25FD
25FE
Mnemonic
Processor
Cycles
8
(2
p
+23)*
r
(2
p
+23)*
r
(2
p
+23)*
r
Name
DEF
move2dinit
move2dall
move2dnonzero
initialise data for 2D block move
2D block copy
2D block copy non-zero bytes
2D block copy zero bytes
Table 11.21
2D block move operation codes