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| 型號： | IMST425G20S |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁數(shù)： | 9/74頁 |
| 文件大小： | 563K |
| 代理商： | IMST425G20S |
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3 System services
/ 74
9
3.7
Reset
can go high with
VDD
, but must at no time exceed the maximum specified voltage for
VIH
. After
VDD
isvalid
ClockIn
shouldberunningforaminimumperiod
TDCVRL
beforetheendof
Reset
.Thefalling
edge of
Reset
initialises the transputer, triggers the memory configuration sequence andstarts theboot-
strap routine. Link outputs are forced low during reset; link inputs and
EventReq
should be held low.
Memory request (DMA) must not occur whilst
Reset
is high but can occur before bootstrap (page 29).
Reset
Aftertheend of
Reset
therewill bea delay of 144periodsof
ClockIn
(figure 3.3).Following this,the
Mem-
notWrD0
,
MemnotRfD1
and
MemAD2-31
pins will be scanned to check for the existence of a pre-pro-
grammed memory interface configuration (page 31). This lasts for a further 144 periods of
ClockIn
. Re-
gardless of whether a configuration was found, 36 configuration read cycles will then be performed on
external memory using the default memory configuration (page 33), in an attempt to access the external
configuration ROM. A delay will then occur,its period dependingon the actual configuration.Finally eight
complete and consecutiverefresh cycleswill initialise anydynamic RAM, using thenew memory configu-
ration. If the memory configuration does not enable refresh of dynamic RAMthe refresh cycles willbe re-
placed by an equivalent delay with no external memory activity.
If
BootFromROM
is high bootstrapping will then take place immediately, using data from external
memory; otherwisethe transputer willawait an inputfromany link. The processorwillbe inthe lowpriority
state.
Reset
Action
Delay
Internal
configuration
External
configuration
Delay
Refresh
Boot
Figure 3.3
IMS T400 post–reset sequence
3.8
Analyse
If
Analyse
is taken high when the transputer is running, the transputer will halt at the next descheduling
point (page 64). From
Analyse
being asserted, the processorwill halt within three time slice periodsplus
the time taken for any high priority process to complete. As much of the transputer status is maintained
as is necessary to permit analysis of the halted machine.
Processor flags
Error
,
HaltOnError
and
EnableJ0Break
are normally cleared at reset on the IMS T400;
however, if
Analyse
is asserted the flags are not altered. Memory refresh continues.
Input links will continue with outstanding transfers.Output linkswill not make another access to memory
for data but willtransmit only those bytes already in the link buffer.Providing there is no delay in link ac-
knowledgement, the links should be inactive within a few microseconds of the transputer halting.
Reset
should notbeasserted before thetransputer has haltedand linktransfers have ceased.When
Re-
set
is taken lowwhilst
Analyse
is high, neither the memory configuration sequence nor the blockof eight
refresh cycles will occur; the previous memory configuration will be used for any external memory ac-
cesses.If
BootFromROM
is highthetransputer willbootstrapas soonas
Analyse
is takenlow,otherwise
itwill awaita controlbyteon anylink. If
Analyse
is takenlow without
Reset
going highthetransputerstate
and operation areundefined.Afterthe endof a valid
Analyse
sequence theregisters havethevalues giv-
en in table 3.3.
I
MemStart
if bootstrappingfromalink, ortheexternalmemorybootstrap addressifbootstrapping
from ROM.
MemStart
if bootstrapping from ROM, or the address of the first free word after the bootstrap
program if bootstrapping from link.
The value of
I
when the processor halted.
The value of
W
when the processor halted, together with the priority of the process when the
transputer was halted (i.e. the
W
descriptor).
The ID of the bootstrapping link if bootstrapping from link.
Table 3.3
Register values after Analyse
W
A
B
C
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| IMST425J17S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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