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參數(shù)資料
| 型號(hào)： | IMXHANTROWP |
| 英文描述： | i.MX Applications Processors with Hantro＇s Multimedia Framework |
| 中文描述： | i.MX應(yīng)用處理器與Hantro的多媒體框架 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 653K |
| 代理商： | IMXHANTROWP |
i.MX Application Processors with Hantro’s Multimedia Framework White Paper, Rev. 2
Freescale Semiconductor
3
The ARM920T processor in the i.MX1 has plenty of performance overhead to perform sophisticated multimedia
functions using Hantro's software codec. For instance, running video conference—with viewfinder, MPEG-4
decode, image deblock, image CSC (color space conversion), and MPEG-4 encode-on QCIF (Quarter
CIF-176x144), 15 fps at 64Kbits/sec—uses only about 150 MHz (speeds are approximate) with a 16-bit external
memory bus. A 32-bit external memory bus helps reduce the speed and performance requirements even further, to
about 130 MHz.
In another example, one-way video streaming of QCIF at 30 fps, using MPEG-4 decode, image deblock, and image
CSC, requires just over 100 MHz with a 16-bit memory bus and only about 90 MHz with a 32-bit memory bus.
Both the Hantro codec and the i.MX1 architecture are optimized to provide high performance at low power levels.
So, even though software solutions are often viewed as resource hogs, in this particular case the flexibility of a
software codec doesn't stretch the processor to the limits of its performance capabilities.
i.MX21 and the Hantro Hardware Implementation
The next generation i.MX processor, the i.MX21, includes the ARM926EJ-S core processor operating at speeds
starting at 266 MHz, and is designed to support both 16-bit and 32-bit external memory buses. The i.MX21 also
includes an LCD controller supporting resolutions up to SVGA resolutions, eMMA (enhanced multimedia
accelerator), and a video port.
The i.MX21's eMMA includes the Hantro MPEG-4 hardware and Freescale technology for pre-processing and
post-processing hardware. Utilizing the i.MX21 eMMA for a videophone use case scenario (see below), less than
20 MHz of processor loading may be required to support these functions thereby helping to reduce the overall use
case loading which is described later.
There are distinct advantages offered by the hardware eMMA. All computer intensive encoding and decoding
calculations are executed in hardware, with software only handling the control functions. This means that the
i.MX21 is designed to handle the simultaneous encode and decode of CIF resolution video at 30 fps. This kind of
performance is particularly critical to meet the demanding requirements of real-time 30 fps wireless video
conferencing. The i.MX21 is designed to meet these requirements and does it with resources to spare—resources
that may be used to perform additional activities.
Also, by complementing Hantro's video codec with Freescale's pre-processing and post-processing hardware
technology, the i.MX21 is a unique solution with enhanced multimedia performance. The pre-processing hardware
technology comprises image resizing and CSC between the image sensor and the encoding process. The
post-processing hardware technology comprises everything between decoding and display. The Freescale
technology includes algorithms for deblocking, deringing, and resizing, which contribute to creating a sharper,
clearer image, regardless of format
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| IMZ1 | TRANSISTOR | BJT | PAIR | COMPLEMENTARY | 40V V(BR)CEO | 100MA I(C) | SO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IMXLRM1AL | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MODULE, W/MINI XLR,1U,AL |
| IMXLRM1BK | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MODULE, W/MINI XLR,1U,BK |
| IMXLRM1EI | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MODULE, W/MINI XLR,1U,EI |
| IMXLRM1GY | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MODULE, W/MINI XLR,1U,GY |
| IMXLRM1LA | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MODULE, W/MINI XLR,1U,LA |
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