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參數(shù)資料
| 型號： | IN7472 |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | AND-Gated J-K Master-Slave Flip-Flops with Reset and Clear |
| 中文描述： | 與門控JK主從觸發(fā)器的復位和清除 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 242K |
| 代理商： | IN7472 |
IN7472
DC ELECTRICAL CHARACTERISTICS
over full operating conditions
Symbol
Parameter
Test Conditions
Guaranteed Limit
Min
Unit
Max
V
IK
V
OH
V
OL
I
I
Input Clamp Voltage
V
CC
= min, I
IN
= -10 mA
V
CC
= min, I
OH
=max
V
CC
= min, I
OL
=max
V
CC
= max, V
IN
= 5.5 V
-1.5
V
High Level Output Voltage
2.4
V
Low Level Output Voltage
0.4
V
Input Current at Maximum
Input Voltage
1
mA
D, J, K
40
I
IH
High Level
Clear
V
CC
= max, V
IN
= 2.4 V
80
μ
A
Input Current
Reset
80
Clock
80
D, J, K
-1.6
I
IL
Low Level
Clear
V
CC
= max, V
IN
= 0.4 V
-3.2
mA
Input Current
Reset
-3.2
Clock
-3.2
I
OS
*
I
CC
Short-Circuit Output Current
V
CC
= max
V
CC
= max, See Note 1
-18
-55
mA
Supply Current
20
mA
*Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
Note 1: With outputs open, I
CC
is measured with the Q and Q outputs high in turn. At the time of measurement, the
clock input is grounded.
3
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