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參數(shù)資料
| 型號(hào)： | IN74AC02D |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Quad 2-Input NOR Gate High-Speed Silicon-Gate CMOS |
| 中文描述： | 四2輸入或非門(mén)高速硅柵CMOS |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | IN74AC02D |
IN74AC02
13
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
V
Guaranteed Limits
25
°
C
Symbol
Parameter
Test Conditions
-40
°
C to
85
°
C
2.1
3.15
3.85
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V
3.0
4.5
5.5
2.1
3.15
3.85
V
V
IL
Maximum Low -
Level Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
3.0
4.5
5.5
0.9
1.35
1.65
0.9
1.35
1.65
V
V
OH
Minimum High-Level
Output Voltage
I
OUT
≤
-50
μ
A
3.0
4.5
5.5
2.9
4.4
5.4
2.9
4.4
5.4
V
*
V
IN
= V
IL
I
OH
=-12 mA
I
OH
=-24 mA
I
OH
=-24 mA
I
OUT
≤
50
μ
A
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
V
OL
Maximum Low-Level
Output Voltage
3.0
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
*
V
IN
= V
IL
or V
IH
I
OL
=12 mA
I
OL
=24 mA
I
OL
=24 mA
V
IN
=V
CC
or GND
3.0
4.5
5.5
0.36
0.36
0.36
±
0.1
0.44
0.44
0.44
±
1.0
I
IN
Maximum Input
Leakage Current
5.5
μ
A
I
OLD
+Minimum Dynamic
Output Current
V
OLD
=1.65 V Max
5.5
75
mA
I
OHD
+Minimum Dynamic
Output Current
V
OHD
=3.85 V Min
5.5
-75
mA
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
5.5
4.0
40
μ
A
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
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| IN74AC02N | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 2-Input NOR Gate High-Speed Silicon-Gate CMOS |
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| IN74AC08 | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 2-Input AND Gate High-Speed Silicon-Gate CMOS |
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