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參數(shù)資料
| 型號： | IN74AC193N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 元件分類： | 通用總線功能 |
| 英文描述： | PRESETTABLE 4 - BIT BINARY UP / DOWN COUNTER HIGH - SPEED SILICON - GATE CMOS |
| 中文描述： | 預置4 -位二進制加/減計數(shù)器高速-高速硅-柵CMOS |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 350K |
| 代理商： | IN74AC193N |
IN74AC193
291
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC
V
*
Guaranteed Limits
25
°
C
Min
Max
Symbol
Parameter
-40
°
C to 85
°
C
Min
Unit
Max
f
max
Maximum Clock Frequency (Figure 1)
3.3
5.0
88
120
40
55
MHz
t
PLH
Propagation Delay, CP
U
or CP
D
to TC
U
or
TC
D
(Figure 2)
Propagation Delay, CP
U
or CP
D
to TC
U
or
TC
D
(Figure 2)
Propagation Delay, CP
U
or CP
D
to Q
n
(Figure
1)
3.3
5.0
20
13
22
14.5
ns
t
PHL
3.3
5.0
19
11.5
21
13.0
ns
t
PLH
3.3
5.0
15
10
17.0
11.5
ns
t
PHL
Propagation Delay, CP
U
or CP
D
to Q
n
(Figure
1)
3.3
5.0
15
9.5
17.0
11
ns
t
PLH
Propagation Delay, P
n
to Q
n
(Figure 3)
3.3
5.0
15
10
17.0
11.5
ns
t
PHL
Propagation Delay, P
n
to Q
n
(Figure 3)
3.3
5.0
15
9.5
17.0
11
ns
t
PLH
Propagation Delay, PL to Q
n
(Figure 4)
3.3
5.0
15
10
17
11.5
ns
t
PHL
Propagation Delay, PL to Q
n
(Figure 4)
3.3
5.0
20
12.5
22
14
ns
t
PHL
Propagation Delay, MR to Q
n
(Figure 5)
3.3
5.0
20
12.5
22
14
ns
t
PLH
Propagation Delay, MR to TC
U
(Figure 6)
3.3
5.0
18
12
20
13.5
ns
t
PHL
Propagation Delay, MR to TC
D
(Figure 6)
3.3
5.0
19
11.5
21
13.0
ns
t
PLH
Propagation Delay, PL to TC
U
or TC
D
(Figure
6)
3.3
5.0
20
13
22
14.5
ns
t
PHL
Propagation Delay, PL to TC
U
or TC
D
(Figure
6)
3.3
5.0
15
8.5
17
10
ns
t
PLH
Propagation Delay, P
n
to TC
U
or TC
D
(Figure
6)
3.3
5.0
20
13
22
14.5
ns
t
PHL
Propagation Delay, P
n
to TC
U
or TC
D
(Figure
6)
3.3
5.0
20
12.5
22
14
ns
C
IN
Maximum Input Capacitance
5.0
4.5
4.5
pF
Typical @25
°
C,V
CC
=5.0 V
45
C
PD
Power Dissipation Capacitance
pF
*
Voltage Range 3.3 V is 3.3 V
±
0.3 V
Voltage Range 5.0 V is 5.0 V
±
0.5 V
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