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參數(shù)資料
| 型號： | IN74HC4015N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual 4-Bit Shift Register High-Performance Silicon-Gate CMOS |
| 中文描述： | 雙4位移位寄存器高性能硅柵CMOS |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IN74HC4015N |
IN74HC4015
477
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
25
°
C to
-55
°
C
6
30
35
Symbol
Parameter
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figure 2)
2.0
4.5
6.0
4.8
24
28
4
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 2 and 5)
2.0
4.5
6.0
175
30
220
44
37
265
53
45
ns
t
PHL
Maximum Propagation Delay, Reset to Q (Figures
1 and 5)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Latch)
Typical @25
°
C,V
CC
=5.0 V
140
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC
2
f+I
CC
V
CC
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
25
°
C to
-55
°
C
50
10
9.0
Symbol
Parameter
≤
85
°
C
≤
125
°
C
Unit
t
su
Minimum Setup Time, D to Clock
(Figure 4)
2.0
4.5
6.0
65
13
11
75
15
13
ns
t
h
Minimum Hold Time, Clock to D
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
rec
Minimum Recovery Time, Reset to
Clock (Figure 1)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
w
Minimum Pulse Width, Reset (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Clock (Figure
4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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