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參數(shù)資料
| 型號： | IN74HCT74AD |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 雙D觸發(fā)器的設置和復位高性能硅柵CMOS |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 100K |
| 代理商： | IN74HCT74AD |
IN74HCT74A
87
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%,C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
25
°
C
to
-55
°
C
30
Symbol
Parameter
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
24
20
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
24
30
36
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Set or Reset to Q or
Q (Figures 2 and 4)
24
30
36
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
C
IN
Maximum Input Capacitance
10
10
10
pF
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
130
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%,C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
≤
85
°
C
Symbol
Parameter
25
°
C to-55
°
C
15
≤
125
°
C
22
Unit
t
su
Minimum Setup Time, Data to Clock
(Figure 3)
19
ns
t
h
Minimum Hold Time, Clock to Data
(Figure 3)
3
3
3
ns
t
rec
Minimum Recovery Time, Set or
Reset Inactive to Clock (Figure 2)
6
8
9
ns
t
w
Minimum Pulse Width, Clock (Figure
1)
15
19
22
ns
t
w
Minimum Pulse Width, Set or Reset
(Figure 2)
15
19
22
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
ns
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|---|---|
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| IN74HCU04 | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Hex Unbuffered Inverter High-Performance Silicon-Gate CMOS |
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