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參數(shù)資料
| 型號： | IN74LV164N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-SO -40 to 85 |
| 中文描述： | 8位SERIAL-IN/PARALLEL-OUT移位寄存器 |
| 文件頁數(shù)： | 6/6頁 |
| 文件大?。?/td> | 45K |
| 代理商： | IN74LV164N |
IN74LV164
6
INTEGRAL
CHIP PAD DIAGRAM
Location of marking (mm):
left lower corner x= 0.960, y= 0.130.
Chip thickness:
0.46
±
0.02 (0.35
±
0.02) mm.
PAD LOCATION
Location (left lower corner), mm
X
1.172
1.486
1.486
1.486
1.486
1.486
0.978
0.440
0.127
0.127
0.127
0.127
0.127
0.635
Pad No
Symbol
Y
Pad size, mm
01
02
03
04
05
06
07
08
09
10
11
12
13
14
DSA
DSB
Q0
Q1
Q2
Q3
GND
CP
MR
Q4
Q5
Q6
Q7
V
CC
0.131
0.131
0.363
0.531
0.689
0.885
0.885
0.885
0.885
0.653
0.485
0.326
0.131
0.131
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
0.100 0.100
Note: Pad location is given as per passivation layer
02
(0,0)
X
Y
Chip marking
LV164
03
04
05
06
07
08
09
10
1.71 + 0.03
1
11
12
01
14
13
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