參數(shù)資料
型號(hào): INA-34063
英文描述: 3.0 GHz Medium Power Silicon RFIC Amplifier(3.0 GHz中等功率硅射頻集成電路放大器)
中文描述: 3.0 GHz的中功率硅射頻放大器(3.0千兆赫中等功率硅射頻集成電路放大器)
文件頁(yè)數(shù): 5/11頁(yè)
文件大?。?/td> 80K
代理商: INA-34063
5
INA-34063 Applications
Information
Introduction
The INA-34063 is a +3 volt silicon
RFIC amplifier that is designed
with a two stage internal network
to provide a broadband gain and
50
input and output impedance.
With a P
-1dB
compressed output
power of 8 dBm and noise figure
of 4.5 dB at 1900 MHz, the
INA-34063 is well suited for
amplifier applications in mobile
communication.
A feature of the INA-34063 is a
positive gain slope over the
1–2 GHz range that is useful in
many satellite-based TV and
datacom systems.
In addition to use in TV delivery
systems, the INA-34063 will find
many applications in battery
operated wireless communication
systems.
Operating Details
The INA-34063 is a voltage-biased
device that operates from a
+3 volt power supply with a
typical current drain of 30 mA. All
bias regulation circuitry is
integrated into the RFIC.
Figure 10 shows a typical imple-
mentation of the INA-34063. The
supply voltage for the INA-34063
must be applied to two terminals,
the V
d
pin and the RF Output pin.
RF
Output
RF
Input
V
d
C
bypass
C
out
C
block
3
RFC
Gnd2
Gnd1
Gnd1
Figure 10. Basic Amplifier
Application.
The V
d
connection to the ampli-
fier is RF bypassed by placing a
capacitor to ground near the V
d
pin of the amplifier package.
The power supply connection to
the RF Output pin is achieved by
means of a RF choke (inductor).
The value of the RF choke must
be large relative to 50
in order
to prevent loading of the RF
Output. The supply voltage end of
the RF choke is bypassed to
ground with a capacitor. If the
physical layout permits, this can
be the same bypass capacitor that
is used at the V
d
terminal of the
amplifier.
Blocking capacitors are normally
placed in series with the RF Input
and the RF Output to isolate the
DC voltages on these pins from
circuits adjacent to the amplifier.
The values for the blocking and
bypass capacitors are selected to
provide a reactance at the lowest
frequency of operation that is
small relative to 50
.
Example Layout for 50
Output Amplifier
An example layout for an ampli-
fier using the INA-34063 with
50
input and 50
output is
shown in Figure 11.
RF Output
and Vd
Gnd 1
RF Input
Gnd 1
Gnd 2
50
50
Figure 11. RF Layout.
This example uses a
microstripline design (solid
groundplane on the backside of
the circuit board). The circuit
board material is 0.031-inch thick
FR-4. Plated through holes (vias)
are used to bring the ground to
the topside of the circuit where
needed. The performance of
INA-34063 is sensitive to ground
path inductance. The two-stage
design creates the possibility of a
feedback loop being formed
through the ground returns of the
stages, Gnd 1 and Gnd 2.
Gnd 1
Gnd 2
VIA
Figure 12. INA-34063 Potential
Ground Loop.
Gnd 1
Gnd 2
VIA
VIA
Figure 13. INA-34063 Suggested
Layout.
At least one ground via should be
placed adjacent to each ground
pin to assure good RF grounding.
Multiple vias are used to reduce
the inductance of the path to
ground and should be placed as
close to the package terminals as
practical.
The effects of the potential
ground loop shown in Figure 12
may be observed as a “peaking” in
the gain versus frequency
response, an increase in input
VSWR, or even as return gain at
the input of the INA-34063.
Figure 14 shows an assembled
amplifier. The +3 volt supply is
fed directly into the V
d
pin of the
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