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參數(shù)資料
| 型號(hào)： | INA103 |
| 元件分類： | 測(cè)量放大器 |
| 英文描述： | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 中文描述： | 單電源，軌至軌，低成本儀表放大器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 297K |
| 代理商： | INA103 |
INA103
9
Accuracy and TCR of the external R
will also contribute to
gain error and temperature drift. These effects can be di-
rectly inferred from the gain equation.
Connections available on A
1
and A
2
allow external resistors
to be substituted for the internal 3k
feedback resistors. A
precision resistor network can be used for very accurate and
stable gains. To preserve the low noise of the INA103, the
value of external feedback resistors should be kept low.
Increasing the feedback resistors to 20k
would increase
noise of the INA103 to approximately 1.5nV/
√
Hz. Due to
the current-feedback input circuitry, bandwidth would also
be reduced.
NOISE PERFORMANCE
The INA103 provides very low noise with low source
impedance. Its 1nV/
√
Hz voltage noise delivers near theo-
retical noise performance with a source impedance of 200
.
Relatively high input stage current is used to achieve this
low noise. This results in relatively high input bias current
and input current noise. As a result, the INA103 may not
provide best noise performance with source impedances
greater than 10k
. For source impedance greater than 10k
,
consider the INA114 (excellent for precise DC applica-
tions), or the INA111 FET-input IA for high speed applica-
tions.
OFFSET ADJUSTMENT
Offset voltage of the INA103 has two components: input
stage offset voltage is produced by A
and A
; and, output
stage offset is produced by A
. Both input and output stage
offset are laser trimmed and may not need adjustment in
many applications.
FIGURE 2. Input Stabilization Network.
FIGURE 3. Offset Adjustment Circuit.
GAIN
GAIN (dB)
R
G
(
)
Note 1
2774
667
196
60.6
(2)
19
6
1
0
3.16
10
31.6
100
316
1000
10
20
30
40
50
60
NOTES: (1) No R
G
required for G = 1.
See gain-set connections in Figure 4.
(2) R
for G = 100 is internal. See
gain-set connection in Figure 5.
FIGURE 1. Basic Circuit Configuration.
Offset voltage can be trimmed with the optional circuit
shown in Figure 3. This offset trim circuit primarily adjusts
the output stage offset, but also has a small effect on input
stage offset. For a 1mV adjustment of the output voltage, the
input stage offset is adjusted approximately 1
μ
V. Use this
adjustment to null the INA103’s offset voltage with zero
differential input voltage. Do not use this adjustment to null
offset produced by a sensor, or offset produced by subse-
quent stages, since this will increase temperature drift.
To offset the output voltage without affecting drift, use the
circuit shown in Figure 4. The voltage applied to pin 7 is
summed at the output. The op amp connected as a buffer
provides a low impedance at pin 7 to assure good common-
mode rejection.
Figure 5 shows a method to trim offset voltage in AC-
coupled applications. A nearly constant and equal input bias
current of approximately 2.5
μ
A flows into both input termi-
nals. A variable input trim voltage is created by adjusting the
balance of the two input bias return resistances through
which the input bias currents must flow.
11
16
7
V
OUT
1
50
50
1.2μH
1.2μH
INA103
1110
7
R
G
V
IN
+
16
15
13
14
6
2
1
R
L
INA103
V
O
= G V
IN
8
+
V–
–
+
9
V+
1μF Tantalum
11
10
7
R
G
V
IN
16
15
13
14
6
2
1
INA103
V
OUT
3
4
10k
V–
Offset Adjust
Range = ±250mV.
G = 1 +6k
R
G
RTI
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