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INA337, INA338
SBOS222A
12
www.ti.com
2k
200k
200k
V
REF
R
O
5
C
O
C
2
V
REF
INA337
A/D
Converter
G = 2(200k
|| 200k
)/2k
= 100
FIGURE 6. Output Range Pedestal.
FIGURE 7. High-Side Shunt Measurement of Current Load.
FILTERING
Filtering can be adjusted through selection of R
2
C
2
and
R
O
C
O
for the desired tradeoff of noise and bandwidth. Adjust-
ment of these components will result in more or less ripple
due to auto-correction circuitry noise and will also affect
broadband noise. Filtering limits slew rate, settling time, and
output overload recovery time.
It is generally desirable to keep the resistance of R
O
relatively
low to avoid DC gain error created by the subsequent stage
loading. This may result in relatively high values for C
O
to
produce the desired filter response. The impedance of R
O
C
O
can be scaled higher to produce smaller capacitor values if
the load impedance is very high.
Certain capacitor types greater than 0.1
μ
F may have dielec-
tric absorption effects that can significantly increase settling
time in high-accuracy applications (settling to 0.01%). Polypro-
pylene, polystyrene, and polycarbonate types are generally
good. Certain
“
high-K
”
ceramic types may produce slow
settling
“
tails.
”
Settling time to 0.1% is not generally affected
by high-K ceramic capacitors. Electrolytic types are not
recommended for C
2
and C
O
.
INA338 ENABLE FUNCTION
The INA338 can be enabled by applying a logic
“
High
”
voltage level to the Enable pin. Conversely, a logic
“
Low
”
voltage level will disable the amplifier, reducing its supply
current from 2.4mA to typically 2
μ
A. For battery-operated
applications, this feature may be used to greatly reduce the
average current and extend battery life. This pin should be
connected to a valid high or low voltage or driven, not left
open circuit. The Enable pin can be modeled as a CMOS
input gate as in Figure 5.
R
1
R
′
2
5
R
0
R
2
C
2
C
0
V
REF
= 10V to 5V
G = 2 (R
2
|| R
′
2
)/R
1
INA337
R
and R
′
are chosen to
create a small pedestal
voltage (e.g., 250mV).
Gain is determined by
the parallel combination
of R
2
and R
′
2
.
INA337
+5V
I
L
5
R
O
R
S
R
1
R
2
C
2
C
O
NOTE: Connection point
of V+ will include ( ) or
exclude ( ) quiescent
current in the measurement
as desired. Output pedestal
required for measurements
near zero (see Figure 6).
R
must be chosen
so that the input voltage
does not exceed 100mV
above the rail.
FIGURE 8. Output Referenced to V
REF
/2.
FIGURE 5. Enable Pin Model.
V+
Enable
6
2
μ
A
V
–
The enable time following shutdown is 75
μ
s plus the settling
time due to filters (see Typical Characteristics,
“
Input Offset
Voltage vs Warm-up Time
”
). Disable time is 100
μ
s. This
allows the INA338 to be operated as a
“
gated
”
amplifier, or
to have its output multiplexed onto a common output bus.
When disabled, the output assumes a high-impedance state.
INA338 PIN 5
Pin 5 of the INA338 should be connected to V+ to ensure
proper operation.