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參數(shù)資料
| 型號： | INTEGRA |
| 英文描述： | Integra L64754 ISDB-S DVB/DSS Satellite Receiver |
| 中文描述： | INTEGRA的L64754的ISDB - ?的DVB / DSS的衛(wèi)星接收機 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 29K |
| 代理商： | INTEGRA |
OV ERV IEW
The L64754 is a satellite receiver demodulator designed specifically to
meet the needs of Japanese satellite broadcast digital TV. Providing maximum
integration and flexibility for system designers at a minimum cost, the L64754
chip reduces the number of external components required to build a system.
LSI Logic fabricates the L64754 using its G12, 1.8 core/ 3.3 volt I/ O, 0. I 8-
micron, HCMOS process technology.
The L64754 demodulator interfaces with any tuner IC, which directly down-
converts satellite signal from L-band to baseband, and includes an on-chip synthesizer
controller. The L64754 generates control signals for a tuner IC synthesizer (using
frequency information programmed into the L64754 configuration registers), and
generates dual AGC control voltages for the two-stage automatic gain control on a
tuner IC chip.
The L64754 satellite demodulator contains two main blocks: a
BPSK/ QPSK/ 8PSK demodulator and a concatenated FEC decoder.
The B/ Q/ 8PSK demodulator performs demodulation for any of the three
modulation formats, a method of extracting a digital signal from a phase-modulated
analog signal. The B/ Q/ 8PSK module is designed specifically for a satellite
broadcast digital TV receiver, and is compliant with the Japanese ISDB-S standard.
The demodulator works as per the European digital video broadcast (DVB-S)
standard and the technical specifications for DSS systems.
Integra
DVB/DSS Satellite Receiver
TM
L64754 ISDB-S
Integra L64754 Block Diagram
ToTuner IC
AGC
Contro
Carrier
LoopContro
Tmmg
LoopContro
Matched
Filter
Output
Contro
Linear
Eq
Dual
ADC
Interpoator /DecmationFilter
External Mcrocontroler Data andAddress Bus
Synthesizer
Contro
Lowpass Filter
Contro
Mcrocontroler Data andAddress Bus
Mcrocontroler Data andAddress Bus
B/Q8PSK
Demoduator
FECDecoder
Ppeline
Channel
Output
(MPEG2)
Transport
Stream
N/T"
ToTuner IC
ToTuner IC
Channel Imput
FromTuner IC
I
Q
Ck (fromL64754
onchpPLL)
Out, Interface
ReedSoomon
Decoder
Bock
Deinterleaver
andFrame Data
Descramber
TMCC
Descramber
Pragmatic
TCMDecoder
TMCCContro
DEM
1/T
DEMQ
The
Communica tions
Compa ny
TM
FEATURES
On-chip dual differential 6-bit
A/ D converters
Variable data rate of 1 to 45
Mbaud
Serial host interface compatible
with the LSI Logic serial control
bus interface
Correction for Quadrature
phase, amplitude imbalance
Integrated PLL for clock synthesis
for use of fundamental mode
crystal
Fast channel-switching mode
Anti-aliasing filters
On-chip digital clock
synchronization
Programmable matched filter
Synthesizer control-programmable
counters
Power estimation for AGC
control-dual AGC outputs to
allow two-stage AGC
On-chip C/ N, BER estimators
Bit-error monitoring for channel
performance measurements for
all possible ISDB-S/ DVB/ DSS
rates
On-chip block de-interleaver
Power-down and Standby
modes
On-chip controller frees host
processor
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