參數(shù)資料
型號(hào): INTEL386 CXSA
廠商: Intel Corp.
英文描述: 5-V 32-Bit Fully Static Embedded Microprocessor(5V,32位完全靜態(tài)嵌入式微處理器)
中文描述: 5V的32位嵌入式微處理器完全靜態(tài)(5V的,32位完全靜態(tài)嵌入式微處理器)
文件頁(yè)數(shù): 7/21頁(yè)
文件大?。?/td> 265K
代理商: INTEL386 CXSA
Intel386 CXSA EMBEDDED MICROPROCESSOR
7
SMI#
(Note 1)
I
44
System Management Interrupt
invokes System Manage-
ment Mode (SMM). SMI# is the highest priority interrupt. It is
latched on its falling edge and it forces the CPU into SMM
upon completion of the current instruction. SMI# is recognized
on an instruction boundary and at each iteration for repeat
string instructions. SMI# cannot interrupt LOCKed bus cycles
or a currently executing SMM. If the processor receives a sec-
ond SMI# while it is in SMM, it will latch the second SMI# on
the SMI# falling edge. However, the processor must exit SMM
by executing a Resume instruction (RSM) before it can ser-
vice the second SMI#.
System Management Interrupt Active
indicates that the
processor is operating in System Management Mode (SMM).
It is asserted when the processor initiates an SMM sequence
and remains asserted (low) until the processor executes the
Resume instruction (RSM).
Write/Read
indicates whether the current bus cycle is a write
cycle or a read cycle. When W/R# is high, the bus cycle is a
write cycle; when W/R# is low, it is a read cycle.
System Power
provides the nominal DC supply input.
SMIACT#
(Note 1)
O
43
W/R#
O
25
V
CC
P
8–10, 21, 32,
39, 42, 48, 57,
69, 71, 84, 91,
97
2, 5, 11–14, 22
35, 41, 49–50,
63, 67–68,
77–78, 85, 98
V
SS
G
System Ground
provides the 0V connection from which all
inputs and outputs are measured.
Table 2. Pin Descriptions
(Continued)
Symbol
Type
Pin
Name and Function
NOTES:
1. This pin supports the additional features of the Intel386 CXSA microprocessor; it is not present on the Intel386 SXSA microprocessor.
2. The A25:24 pins support the additional features of the Intel386 CXSA microprocessor; they are not present on the Intel386 SXSA micro-
processor.
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