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Intel387
TM
DX MATH COPROCESSOR
Instruction
Optional
Fields
First Byte
Second Byte
1
11011
OPA
1
MOD
1
OPB
R/M
SIB
DISP
2
11011
MF
OPA
MOD
OPB
R/M
SIB
DISP
3
11011
d
P
OPA
1
1
OPB
ST(i)
4
11011
0
0
1
1
1
1
OP
5
11011
0
1
1
1
1
1
OP
15–11
10
9
8
7
6
5
4
3
2
1
0
5.0 Intel387
TM
DX MCP EXTENSIONS
TO THE Intel386
TM
DX CPU
INSTRUCTION SET
Instructions for the Intel387 DX MCP assume one of
the five forms shown in the following table. In all
cases, instructions are at least two bytes long and
begin with the bit pattern 11011B, which identifies
the ESCAPE class of instruction. Instructions that
refer to memory operands specify addresses using
the Intel386 DX CPU addressing modes.
OP
e
Instruction opcode, possible split into two
fields OPA and OPB
MF
e
Memory Format
00D32-bit real
01D32-bit integer
10D64-bit real
11D16-bit integer
P
e
Pop
0DDo not pop stack
1DPop stack after operation
ESC
e
11011
d
e
Destination
0DDestination is ST(0)
1DDestination is ST(i)
R XOR d
e
0DDestination (op) Source
R XOR d
e
1DSource (op) Destination
ST(i)
e
Register stack element i
000
e
Stack top
001
e
Second stack element
#
#
#
111
e
Eighth stack element
MOD (Mode field) and R/M (Register/Memory spec-
ifier) have the same interpretation as the corre-
sponding fields of the Intel386 DX Microprocessor
instructions (refer to Intel386
TM
DX Microprocessor
Programmer’s Reference Manual).
SIB (Scale Index Base) byte and DISP (displace-
ment) are optionally present in instructions that have
MOD and R/M fields. Their presence depends on
the values of MOD and R/M, as for Intel386 DX Mi-
croprocessor instructions.
The instruction summaries that follow assume that
the instruction has been prefetched, decoded, and is
ready for execution; that bus cycles do not require
wait states; that there are no local bus HOLD re-
quest delaying processor access to the bus; and
that no exceptions are detected during instruction
execution. If the instruction has MOD and R/M fields
that call for both base and index registers, add one
clock.
36
36