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| 型號(hào)： | IP1843J |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 69K |
| 代理商： | IP1843J |
t
c
≈
0.55 R
T
C
T
t
d
≈
R
T
C
T
R
n
1
Resultant frequency f =(t
c
+ t
d
)
For R
T
> 5k
,
1.8
Resultant frequency f
≈
(R
T
C
T
)
LAB
SEME
IP1842A SERIES
IP1843A SERIES
Semelab plc.
Telephone (01455) 556565. Telex: 341927. Fax (01455) 552612.
Prelim. 2/95
Open–Loop Laboratory Test Fixture
APPLICATIONS INFORMATION
Oscillator timing capacitor C
T
is charged by V
REF
through R
T
and discharged by an internal current source.
During the discharge time, the internal clock signal
blanks the output to the low state. Selection of R
T
and
C
T
therefore determines both oscillator frequency and
maximum duty cycle. Charge and discharge times are
determined by the formulae:
High peak current associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should
be connected close to pin 5 in a single point ground. The transistor and 5K potentiometer are used to sample the oscillator wave
form and apply an adjustable ramp to pin 3.
0.1
μ
F
1k
1kW
1k
ERROR AMP
ADJUST
4.7k
5k
I
SENSE
ADJUST
4.7k
100k
2N2222
R
T
C
T
0.1
μ
F
V
REF
V
CC
OUTPUT
GROUND
1
2
4
5
7
8
3
6
I
SENSE
V
REF
V
CC
O/P
GND
COMP
V
FB
R
T
/C
T
Oscillator Waveforms and Maximum Duty Cycle
8
4
5
GND
R
T
C
T
REF
V
R
T
C
T
V (V for 14 pin D package)
INTERNAL CLOCK
INTERNAL CLOCK
OUTPUT – Max. Duty Cycle
V (V for 14 pin D package)
V (V for 14 pin D package)
OUTPUT – Max. Duty Cycle
V (V for 14 pin D package)
LARGE C
T
SMALL R
T
LARGE R
T
SMALL C
T
.0063 R
T
– 2.3
.0063 – 4
( )
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