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14
IR1110
ADVANCE INFORMATION
www.irf.com
Operation Description
Overall Functional Diagram
A detailed functional diagram of the IR1110 and peripheral components is shown in Figure 4.
The IR1110 receives signals from the AC input lines U, V, W, and DC bus voltage, DC+, DC-, via
resistor dividers, and delivers line-synchronized pulses SCRU, SCRV, SCRW to external SCR gate
driver circuits. The timing of these pulses controls the DC bus voltage.
The IR1110 also delivers Status Feedback signals, that denote loss of all input phases, loss
of one input phase and low/high AC line voltage.
The
“
ground
”
of the IR1110 is common with the SCR cathodes.
Line Voltage Processing circuit
The inputs to the line voltage processing circuit represent the voltage across the SCRs.
Each of the three outputs of this circuit, RINTU, RINTV, RINTW is a voltage waveform that is
negative over the range of control of firing angle of the associated SCR, and positive outside this
range.
The possible portion only of these waveforms appears at RSTRU, RSTRV, RSTRW.
Timing Wave Integrators
Each Timing Wave Integrator integrates the negative portions of the output waveforms of
the Line Voltage Processing circuit, via R
INT
, and the positive portions, via R
INT
and R
INTR
in
parallel.
The outputs, CINTU, CINTV, CINTW are a set of line synchronized
“
sawtooth
”
timing
waves. These have the desired phase relationship to the line voltages, so that intersection of
these waves with the Timing Wave Reference defines the SCR firing instants. See Figure 5.
V
PKL-L
Store
Voltages U
IN
-V
IN
, V
IN
-W
IN
, W
IN
-U
IN
are rectified and the peak value, proportional to the
peak line voltage, is stored on C
PKLL
. The time constant of R
PKLL1
and R
PKLL2
with C
PKLL
allows
V
PLL
to track changes of line voltage that take place over a number of cycles, while maintaining an
essentially smooth waveform.
Watchdog
The watchdog resets the Timing Wave Integrator within a few milliseconds of the normal
reset point, should an abnormality in the line voltage waveshapes, such as one or all input phases
missing, prevent resetting at the normal time.
In the normal operation, the watchdog circuit plays only a passive role.