參數(shù)資料
型號(hào): IR1150ISTRPBF
廠商: International Rectifier
文件頁(yè)數(shù): 9/16頁(yè)
文件大小: 919K
描述: IC PFC CONTROLLER CCM 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
模式: 連續(xù)導(dǎo)電(CCM)
頻率 - 開(kāi)關(guān): 200kHz
電流 - 啟動(dòng): 175µA
電源電壓: 15 V ~ 20 V
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 帶卷 (TR)
       IR1150(S)/IR1150I(S)(PbF)
www.irf.com 
 
 
 
9
 
Operating States 
 
UVLO Mode 
 
The IC remains in the UVLO condition until the voltage on
the V
CC
  pin exceeds the VCC turn on threshold voltage,
VCC ON.
During the time the IC remains in the UVLO state, the gate
drive circuit is inactive and the IC draws a
quiescent current of ICC START. The UVLO mode is
accessible from any other state of operation whenever the
IC supply voltage condition of V
CC
 < V
CC
 
UVLO
 occurs.
 
Standby Mode 
 
The IC is in this state if the supply voltage has exceeded
V
CC ON
 and the VFB pin voltage is less than 20% of VREF .
The oscillator is running and all internal circuitry is biased
in this state but the gate is inactive. This state is
accessible from any other state of operation except OVP.
The IC enters this state whenever the VFB pin voltage has
decreased to 50% of VREF when operating in normal
mode or during a peak current limit fault condition, or 20%
VREF when operating in soft start mode.
 
Soft Start Mode 
This state is activated once the V
CC
  voltage has
exceeded V
CCON
  and the VFB pin voltage has exceeded
20% of VREF.
The soft start time, which is defined as the time required
for the duty cycle to linearly increase from zero to
maximum, is dependent upon the values selected for
compensation of the voltage loop pin COMP to pin COM.
Throughout the soft start cycle, the output of the voltage
error    amplifier    (pin    COMP)    charges    through    the
compensation network. This forces a linear rise of the
voltage at this node which in turn forces a linear increase
in the gate drive duty cycle from 0. This controlled duty
cycle reduces system component stress during start up
conditions as the input current amplitude is increasing
linearly.
 
Normal Mode 
 
The IC enters normal operating mode once the soft start
transition has been completed. At this point the gate drive
is switching and the IC draws a maximum of ICC from the
supply voltage source. The device will initiate another soft
start sequence in the event of a shutdown due to a fault,
which activates the protection circuitry, or if the supply
voltage drops below the UVLO turn off threshold of V
CC
UVLO
.
 
Fault Protection Mode 
 
The fault mode will be activated when any of the protection
circuits are activated. The IC protection circuits include
Supply Voltage Under Voltage Lockout (UVLO), Output
Over Voltage Protection (OVP), Open Loop Protection
(OLP), Output Undervoltage Protection (OUV), and Peak
Current Limit Protection (I
PK LIMIT
).
 
Sleep Mode 
 
The sleep mode is initiated by pulling the OVP pin below
0.62V (typ). In this mode the IC draws a very low
quiescent supply current. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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