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參數(shù)資料
| 型號： | IR2213S |
| 英文描述： | High and Low Side Driver. Noninverting Inputs in a 16-lead SOIC package |
| 中文描述： | 高和低側(cè)驅(qū)動器。同相輸入的16引腳SOIC封裝 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 137K |
| 代理商： | IR2213S |
2
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IR2213(
S
)
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
dVs/dt
P
D
Definition
Min.
-0.3
Max.
1225
Units
High Side Floating Supply Voltage
High Side Floating Supply Offset Voltage
V
B
- 25
V
S
- 0.3
-0.3
V
B
+ 0.3
V
B
+ 0.3
25
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
-0.3
V
CC
+ 0.3
V
SS
+ 25
V
CC
+ 0.3
V
DD
+ 0.3
50
Logic Supply Voltage
-0.3
Logic Supply Offset Voltage
V
CC
- 25
V
SS
- 0.3
—
Logic Input Voltage (HIN, LIN & SD)
Allowable Offset Supply Voltage Transient (Figure 2)
Package Power Dissipation @ T
A
≤
+25°C (14 Lead PDIP)
(16 Lead SOIC)
V/ns
—
1.6
—
1.25
R
THJA
Thermal Resistance, Junction to Ambient (14 Lead PDIP)
—
75
(16 Lead SOIC)
—
100
T
J
T
S
T
L
Junction Temperature
—
125
Storage Temperature
-55
150
Lead Temperature (Soldering, 10 seconds)
—
300
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
Definition
Min.
V
S
+ 12
Note 1
Max.
V
S
+ 20
1200
Units
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
V
S
12
V
B
20
Low Side Fixed Supply Voltage
Low Side Output Voltage
0
V
CC
Logic Supply Voltage
V
SS
+ 3
-5 (Note 2)
V
SS
+ 20
5
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
V
SS
V
DD
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential.
Note 1: Logic operational for V
S
of -5 to +1200V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When V
DD
<5V, the minimum V
SS
offset is limited to -V
DD
°
C/W
W
V
V
°
C
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