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參數(shù)資料
| 型號： | IR3621M |
| 廠商： | International Rectifier |
| 英文描述： | 2-PHASE / DUAL SYNCHRONOUS PWM CONTROLLER WITH OSCILLATOR SYNCHRONIZATION AND PRE-BIAS STARTUP |
| 中文描述： | 2相/雙同步PWM控制器，帶有振蕩器同步操作和預偏置啟動 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大小： | 389K |
| 代理商： | IR3621M |
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16
IR3621 & (PbF)
www.irf.com
Cross Over Frequency:
F
O
= R
7
×
C
10
×
×
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (16) regarding transconduc-
tance error amplifier.
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient response. The DC gain will be large enough to pro-
vide high DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45
!
for overall
stability.
Based on the frequency of the zero generated by ESR
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.
Compensator
Type
Crossover Frequency
(F
O
)
F
LC
< F
ESR
< F
O
< f
S
/2
Where:
V
IN
= Maximum Input Voltage
V
OSC
= Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
V
IN
V
OSC
1
2
π×
Lo
×
Co
---(17)
F
P1
= 0
1
π×
C
10
×
(R
6
+ R
8
)
F
Z2
= 2
1
2
π×
C
10
×
R
6
F
Z1
=
1
2
π×
R
7
×
C
11
F
P3
=
2
π×
R
7
×
1
1
2
π×
R
7
×
C
12
F
P2
=
1
2
π×
R
8
×
C
10
C
12
+C
11
C
12
×
C
11
Details are dicussed in application Note AN-1043 which
can be downloaded from the IR Web-Site.
Type II (PI)
Type III (PID)
Method A
Type III (PID)
Method B
Table - The compensation type and location of zero
crossover frequency.
Location of Zero
F
LC
< F
O
< F
ESR
< f
S
/2
F
LC
< F
O
< f
S
/2 < F
ZO
Typical
Output
Capacitor
Electrolytic,
Tantalum
Tantalum,
Ceramic
Ceramic
The slave error amplifier is a differential-input transcon-
ductance amplifier, in 2-phase configuration the main goal
for the slave feed back loop is to control the inductor
current to match the master's inductor current as well
provides highest bandwidth and adequate phase margin
for overall stability. The following analysis is valid for both
using external current sense resistor and using DCR of
inductors.
Where:
V
IN
= Input Voltage
L
2
= Output Inductor
V
OSC
= Oscillator Peak Voltage
G(s) = Ve(s)
sL
2
×
V
OSC
I
(s)
V
IN
D(s) = Ve(s)
R
S2
×
I
L2
(s)
1 + sC
2
R
2
( )
R
S1
R
S2
( )
g
m
×
×
---(19)
L
2
L
1
C
2
R
2
R
S2
R
S1
Ve
I
L2
I
L1
Fb2
E/A2
Comp2
Vp2
H(s)=[G(s)
×
D(s)
×
R
S2
]
( )
1+sR
2
C
2
sC
2
( )
g
m
×
R
S1
R
S2
( )
sL
2
V
OSC
V
IN
H(s)=R
S2
×
×
×
Compensation for Slave Error Amplfier for 2-Phase
Configuration
The transfer function of power stage is expressed by:
As shown the transfer function is a function of inductor
current.
The transfer function for the compensation network is
given by equation (19), when using a series RC circuit
as shown in Figure 17:
Figure 17 - The PI compensation network
for slave channel.
The loop gain function is:
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