53
8008H–AVR–04/11
ATtiny48/88
A typical and general setup for interrupt vector addresses in ATtiny48/88 is shown in the pro-
gram example below.
Note:
9.2
External Interrupts
The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT[27:0] pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT[27:0] pins
are configured as outputs. This feature provides a way of generating a software interrupt, as
follows.
Pin Change Interrupt PCI3 triggers if a pin in PCINT[27:24] is toggled while enabled
Pin Change Interrupt PCI2 triggers if a pin in PCINT[23:16] is toggled while enabled
Pin Change Interrupt PCI1 triggers if a pin in PCINT[15:8] is toggled while enabled
Pin Change Interrupt PCI0 triggers if a pin in PCINT[7:0] is toggled while enabled
The PCMSK3, PCMSK2, PCMSK1 and PCMSK0 registers control which pins contribute to the
pin change interrupts. Pin change interrupts on PCINT[27:0] are detected asynchronously. This
Assembly Code Example
.org 0x0000
;Set address of next statement
rjmp RESET
; Address 0x0000
rjmp INT0_ISR
; Address 0x0001
rjmp INT1_ISR
; Address 0x0002
rjmp PCINT0_ISR
; Address 0x0003
rjmp PCINT1_ISR
; Address 0x0004
rjmp PCINT2_ISR
; Address 0x0005
rjmp PCINT3_ISR
; Address 0x0006
rjmp WDT_ISR
; Address 0x0007
rjmp TIM1_CAPT_ISR
; Address 0x0008
rjmp TIM1_COMPA_ISR
; Address 0x0009
rjmp TIM1_COMPB_ISR
; Address 0x000A
rjmp TIM1_OVF_ISR
; Address 0x000B
rjmp TIM0_COMPA_ISR
; Address 0x000C
rjmp TIM0_COMPB_ISR
; Address 0x000D
rjmp TIM0_OVF_ISR
; Address 0x000E
rjmp SPI_STC_ISR
; Address 0x000F
rjmp ADC_ISR
; Address 0x0010
rjmp EE_RDY_ISR
; Address 0x0011
rjmp ANA_COMP_ISR
; Address 0x0012
rjmp TWI_ISR
; Address 0x0013
RESET:
; Main program start
<instr>
; Address 0x0038
...