參數(shù)資料
型號(hào): IRAUDAMP7S
廠商: International Rectifier
文件頁(yè)數(shù): 15/17頁(yè)
文件大?。?/td> 0K
描述: BOARD REF DESIGN 2CH AUDIO AMP
標(biāo)準(zhǔn)包裝: 1
放大器類型: D 類
輸出類型: 2 通道(立體聲)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 500W x 1 @ 8 歐姆; 250W x 2 @ 4 歐姆
電源電壓: ±45 V ~ 60 V
工作溫度: -40°C ~ 125°C
板類型: 完全填充
已用 IC / 零件: IRFI4019H,IRS2092
已供物品:
產(chǎn)品目錄頁(yè)面: 1383 (CN2011-ZH PDF)
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IRS2092
7
www.irf.com
2013 International Rectifier
October 24, 2013
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions below. The Vs and COM
offset ratings are tested with supplies biased at VAA-VSS=10 V, VCC=12 V and VB-VS=12 V. All voltage parameters
are absolute voltages referenced to COM; all currents are defined positive into any lead.
Symbol
Definition
Min.
Max.
Units
VB
High side floating supply absolute voltage
VS +10
VS +18
V
VS
High side floating supply offset voltage
200
IAAZ
Floating input positive supply zener clamp current
1
11
mA
ISSZ
Floating input negative supply zener clamp current
1
11
VSS
Floating input supply absolute voltage
0
200
V
VHO
High side floating output voltage
Vs
VB
VCC
Low side fixed supply voltage
10
18
VLO
Low side output voltage
0
VCC
VGND
GND pin input voltage
VSS
VAA
VIN-
Inverting input voltage
VGND -0.5
VGND +0.5
VCSD
CSD pin input voltage
VSS
VAA
VCOMP
COMP pin input voltage
VSS
VAA
CCOMP
COMP pin phase compensation capacitor to GND
1
-
nF
VDT
DT pin input voltage
0
VCC
V
IOREF
Reference output current to COM
0.3
0.8
mA
VOCSET
OCSET pin input voltage
0.5
5
V
VCSH
CSH pin input voltage
Vs
VB
dVss/dt
Allowable Vss voltage slew rate upon power-up
-
50
V/ms
IPW
Input pulse width
10
-
ns
fSW
Switching Frequency
-
800
kHz
TA
Ambient Temperature
-40
125
C
Logic operational for Vs equal to
–5 V to +200 V. Logic state held for Vs equal to –5 V to –V
BS.
Nominal voltage for VREF is 5.1 V. IOREF of 0.3 – 0.8 mA dictates total external resistor value on VREF
to be 6.3 kΩ to 16.7 kΩ.
GND input voltage is limited by IAAZ and ISSZ.
VSS ramps up from 0 V to 200 V.
Output logic status may not respond correctly if input pulse width is smaller than the minimum pulse
width.
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