參數(shù)資料
型號： IRMCV201
廠商： International Rectifier
英文描述： Complete Motion Control Verilog Library Accelerator Verilog Code Development Tool
中文描述： 完整的運(yùn)動控制的Verilog庫加速器Verilog代碼開發(fā)工具
文件頁數(shù)： 1/1頁
文件大小： 136K
代理商： IRMCV201
May 15, 2003 Rev 3.0
IRMCV201
Complete Motion Control Verilog Library
Accelerator
TM
Verilog Code Development Tool
Features
Accelerator
TM
architecture AC servo development
system
ServoDesigner
TM
graphical user interface for
configuration, control and monitoring
Verilog code library grouped into three segments:
FOC blocks
Motion peripheral blocks
Communication blocks
Bilinear transformation based discretization
Rapid prototyping with Accelerator
TM
Hardware
Platform
Product Summary
Flexible Target Silicon
FPGA or ASIC
Field Orientation Control execution 6 usec (200 sysclk)
Versatile PWM module
Sine or Space Vector PWM
Communication options
Fast SPI (5 MHz),
Description
IRMCV201 is a Verilog code development tool including a rich
Verilog library and graphical user interface. The tool set is
designed to facilitate motion control algorithm development
including motion peripheral and communication modules.
Flexible configuration allows the user to quickly realize hardware
on an FPGA to achieve a high performance AC motor control
system.
UART (57.6K or 1Mbit)
PI
PI
θ
j
e
θ
j
e
Quadrature
Decoding
2/3
dt
+
+
Dea
d
time
Space Vector
PWM
IR2175
interface
IR2175
interface
CLK
DATA
BRAKE
FAULT
+
-
-
+
ADS7818
A/D
interface
DC bus dynamic
brake control
I1 x I2
I3
I3
I1
I2
I1 x I2
I3
I3
I1
I2
O
O
I1 x I2
I3
I3
I1
I2
O
0
+
+
PI
6
RAMP
+
-
3
2
CNVST
MUX
2
Optional
Current Sense
Gate
Signals
3
Encoder
A/B/Z
Encoder
Hall A/B/C
Motor
Phase
Current V
Motor
Phase
Current W
Current
Offset W
Current
Offset V
ID scale
IQ scale
4096
4096
VDLIM
- VDLIM
CURKP
CURKI
- VQLIM
VQLIM
IDREF
INT_REF
Velocity
Control
Enable
Reference
Select
Feedforward
path enable
Slip gain
enable
EncType
Accel Rate
Decel
Rate
4096
Slip gain
IQLIM+
IQLIM-
SPDKP
SPDKI
8 channel
Serial
A/D
Interface
EXT_REF
DCV_FDBK
RS232C/
RS422
Interface
SPI
Slave
Interface
START
STOP
DIR
FLTCLR
SYNC
FAULT
PWM ACTIVE
RCV
SND
RTS
CTS
SCK
SDO
SDI
CS
17
Data
Address
Control
Host Register
Interface
Sequence
Control
IQ
ID
IQREF
VD
VQ
VQS
VDS
IV
IW
Parallel
Interface
Configuration
Registers
Monitoring
Registers
MaxEncCount
InitZval
AngleScale
InitZ
Zpol
SpdScale
PWMmode
PWMen
2Pen
GSenseU
GSenseL
ModScl
Dtime
Closed Loop Current Control
Update Rate = PWM carrier frequency x1 or x 2
Closed Loop Velocity Control, Sequencing Control
Update Rate = PWM carrier frequency / 2
Communication Modules
Optional
CurrentSense
VD enable
INT_VD
I1 x I2
I3
I3
I1
I2
O
REF scale
4096
+/-16383 = +/-max_speed
INT_VQ
+/-16383 = +/-4X of rated current for IQ
+/-4095 = +/-rated ID for IM field flux
4ch
DAC module
INT_DAC1
INT_DAC2
INT_DAC3
INT_DAC4
DAC_PWM1
DAC_PWM2
DAC_PWM3
DAC_PWM4
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
1
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