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參數(shù)資料
| 型號： | IS23SC4428 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 1024 x 8 Bits of EEPROM With Programmable Write Protection For Each Byte And Two Bytes of Programmable Security Code(1024 x 8位，每個字節(jié)帶可編程寫保護，2字節(jié)可編程安全密碼的EEPROM) |
| 中文描述： | 1024 × 8位的EEPROM，具有可編程寫保護對于每一個字節(jié)，兩個字節(jié)可編程保障法（1024 × 8位，每個字節(jié)帶可編程寫保護，2字節(jié)可編程安全密碼的EEPROM中） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IS23SC4428 |
IS23SC4418/4428
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
NV001-0C
02/05/99
9
ISSI
IS23SC4428 SECURITY FEATURES
Overview
Without entering Programmable Security Code (PSC), only
memory read access is possible. However, the content of the
PSC addresses (1022 and 1023) cannot be read out. If
reading PSC is attempted, 00H will be output. The PSC
verification procedure must be performed in the following
sequence:
1. Write one to not-written Error Counter bit, address 1021
2. Enter first PSC byte, address 1022
3. Enter second PSC byte, address 1023
4. After successful PSC verification, the Error Counter
should be erased to reactivate the 8 PSC entry attempts.
If the PSC entry is incorrect, go back to step 1. If all the
Error Counter bits have been written, any further PSC
entry will be blocked and trhe memory can never be
changed again.
Writing Error Counter
The number of erased bits (logic 1) in Error Counter determines
the number of possible attempts (maximum of eight). Before
PSC entry, only writing of error counter is possible. After PSC
is successfully verified, the counter can now be erased.
Before disconnecting the supply voltage Vcc, the counter
should be erased in order to reactivate the eight attempts.
(See Figure 10.)
Entry of PSC
The least significant PSC byte beginning with the least
significant bit must be entered first and then the most significant
(see Table 1). If both PSC byte 1's and byte 2's comparisons
prove correct, the memory erase/write access will be enabled
and PSC may be changed as wished, except the
corresponding protect bits are 0 (enabled). (See Figure 11.)
Condition when supplied
IS23SC4428 is supplied by the manufacturer with a 2-byte
PSC (transport security code) which is determined in
cooperation with the customer.
RST
I/O
CLK
E/W
(internal
signal)
Command
Entry
Writing Error Counter
Write
0
S0
D6
23
0
1
2
89
102
…
D7
S1
Figure 10. Writing Error Counter
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IS23SC4428-X2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| IS23SC4428-X2I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| IS23SC4428-X3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| IS23SC4428-X3I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| IS23SC4428-X4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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