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參數(shù)資料
| 型號(hào)： | IS24C16-P |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 16,384-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| 中文描述： | 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | IS24C16-P |
ISSI
IS24C16
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EE001-0C
10/03/97
GENERAL DESCRIPTION
The IS24C16 features a SERIAL communication, and
supports bidirectional data transmission protocol allowing
one IS24C16 operation on a simple two-wire bus. The two-
wire bus is defined as a serial data line (SDA), and a serial
clock line (SCL). (Refer to Figure 1. Typical System Bus
Configuration.)
The protocol defines any device that sends data onto the
SDA bus as a transmitter, and the receiving device as a
receiver. The device controlling the data transmission is
named MASTER device, and the controlled device is
named SLAVE device.
The IS24C16 does not use any device address bits but
instead the three bits are used for memory page address-
ing. These page addressing bits should be considered the
most significant bits of the data word address which
follows. The A0, A1, and A2 pins are no connect.
The eighth bit of the device address is the read/write
operation select bit. A read operation is initiated if this bit
is HIGH and a write operation is initiated if this bit is LOW.
The ACKnowledge is used to indicate successful data
transfers. The transmitting device will release the data bus
(SDA goes HIGH) after transmitting eight bits (one data bit
is transfered at the falling edge of each clock cycle). During
the ninth clock cycle, the receiver will pull the SDA line
LOW to ACKnowledge the transmitter that it received the
eight bits of data. (Refer to Figure 2. ACKnowledge Re-
sponse from Receiver Diagram.)
DEVICE OPERATION
START and STOP Conditions
Both SDA and SCL lines remain HIGH when the SDA bus
is not busy. A HIGH-to-LOW transition of SDA line, while
SCL is HIGH, is defined as the START condition. A LOW-
to-High transition of SDA line, while SCL is HIGH, is
defined as the STOP condition. (Refer to Figure 3. Start
and Stop Conditions.)
Data Validity Protocol
One data bit is transferred during each clock cycle. The
data on the SDA line must remain stable during the HIGH
period of the clock cycle, because changes on SDA line
during the SCL HIGH period will be interpreted as START
or STOP control signals. (Refer to Figure 4. Data Validity
Protocol.)
Device Addressing Byte Definitions
The most significant four bits of Device Addressing Byte
(Bit 7 to Bit 4) are defined as the device type identifier. For
IS24C16, this is fixed as 1010. The next three significant
address bits (Bit 3 to Bit 1) are address memory bits. One
IS24C16 device can be connected on the bus. The last bit
Bit 0 defines the write or read operation to be performed.
When set to “1”, a READ operation is selected; when set
to “0” a WRITE operation is selected. (Refer to Figure 5.
Device Addressing Byte Definitions.)
WRITE OPERATION
Byte Write
For a WRITE operation, the IS24C16 requires another
8-bit data word address following the Device Addressing
Byte and ACKnowledgement. This data word address
provides access to any one of the 256 data words of
device's memory array.
Upon receipt of the data word address, the IS24C16
responds with an ACKnowledge on SDA, and waits for the
next 8-bit data word, then again responding with an
ACKnowledge. The master device terminates the Byte
Write Operation by generating a STOP condition, after-
ward the IS24C16 begins the internal WRITE cycle to the
nonvolatile memory array. Refer to Write Cycle Timing. All
inputs are disabled during this write cycle and the device
will not response to any requests from the master. (Refer
to Figure 6. Write Operation for the Address, ACKnowledge,
and Data Transfer Sequence.)
Page Write
The IS24C16 is capable of 8-byte page- WRITE operation.
A page-WRITE is initiated in the same manner as a byte
write, but instead of terminating the internal write cycle
after the first data word is transfered, the master device
can transmit up to 15 more words. After the receipt of each
data word, the IS24C16 responds immediately with an
ACKnowledge on SDA line, and the four lower order data
word address bits are internally incremented by one while
the four higher order bits of the data word address remain
constant. If the master device should transmit more than
8 words, prior to issuing the STOP condition, the address
counter will “roll over,” and the previously written data will
be overwritten. All inputs are disabled until completion of
the internal WRITE cycle. (Refer to Figure 7. Write Opera-
tion for the Address, ACKnowledge, and Data Transfer
Sequence.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS24C16-2PI | 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C16-3G | 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C16-3GA | 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C16-3GI | 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C16-3P | 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS24C16-PI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16,384-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS24C256 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:262,144-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C256-2G | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:262,144-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C256-2GI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:262,144-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C256-2P | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:262,144-bit 2-WIRE SERIAL CMOS EEPROM |
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