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參數(shù)資料
| 型號： | IS24C52-3G |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| 中文描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 68K |
| 代理商： | IS24C52-3G |
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00B
01/26/04
3
IS24C52
ISSI
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain or
open collector outputs. The SDA bus requiresa pullup
resistor to Vcc.
PIN CONFIGURATION
8-Pin SOIC, TSSOP, MSOP
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software write-
protection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device. If the device has already received a write-protection
command, the memory in the range of 00h-7Fh is read -only
regardless of the setting of the WP pin.
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are
hardwired or left unconnected for hardware flexibility. When
pins are hardwired, as many as eight devices may be
addressed on a single bus system. When the pins are not
hardwired, the default A0, A1, and A2 are zero.
DEVICE OPERATION
The IS24C52 features a serial communication and supports
a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C52 is the Slave device on the bus.
相關(guān)PDF資料 |
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| IS24C52-3GI | 2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3S | 2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3SI | 2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3Z | 2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3ZI | 2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS24C52-3GI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3S | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3SI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3Z | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
| IS24C52-3ZI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection |
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